diff options
Diffstat (limited to 'ip')
35 files changed, 4731 insertions, 0 deletions
diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.asy b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.asy new file mode 100755 index 0000000..83e8d5d --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.asy @@ -0,0 +1,21 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 clkgendcm_720p60hz +RECTANGLE Normal 32 32 576 1088 +LINE Normal 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName clk_in1 +PINATTR Polarity IN +LINE Normal 0 432 32 432 +PIN 0 432 LEFT 36 +PINATTR PinName reset +PINATTR Polarity IN +LINE Normal 608 80 576 80 +PIN 608 80 RIGHT 36 +PINATTR PinName clk_out1 +PINATTR Polarity OUT +LINE Normal 608 944 576 944 +PIN 608 944 RIGHT 36 +PINATTR PinName locked +PINATTR Polarity OUT +
diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.ejp b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.ejp new file mode 100755 index 0000000..b308e6d --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.ejp @@ -0,0 +1,245 @@ +Encore.Project.ProjectDir = C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/tmp/_cg
+Encore.Project.ElaborationDir = C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/tmp/_cg
+Encore.Project.TmpDir = C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/tmp/_cg
+Encore.Project.Path = C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/tmp/_cg
+Encore.Project.FlowVendor = Other
+Encore.Project.VhdlSim = false
+Encore.Project.VerilogSim = true
+Encore.Project.XDevice = xc6slx9
+Encore.Project.XDeviceFamily = spartan6
+Encore.Project.XSpeedGrade = -2
+Encore.Project.XPackage = tqg144
+
+c_use_clkout1_bar = 0
+c_use_clkout2_bar = 0
+c_use_clkout3_bar = 0
+c_use_clkout4_bar = 0
+component_name = clkgendcm_720p60hz
+c_platform = nt64
+c_use_freq_synth = 1
+c_use_phase_alignment = 0
+c_use_min_o_jitter = 0
+c_use_max_i_jitter = 0
+c_use_dyn_phase_shift = 0
+c_use_inclk_switchover = 0
+c_use_dyn_reconfig = 0
+c_use_spread_spectrum = 0
+c_primtype_sel = DCM_CLKGEN
+c_use_clk_valid = 0
+c_prim_in_freq = 26
+c_in_freq_units = Units_MHz
+c_secondary_in_freq = 100.000
+c_feedback_source = FDBK_AUTO
+c_prim_source = No_buffer
+c_secondary_source = Single_ended_clock_capable_pin
+c_clkfb_in_signaling = SINGLE
+c_use_reset = 1
+c_use_locked = 1
+c_use_inclk_stopped = 0
+c_use_power_down = 0
+c_use_status = 0
+c_use_freeze = 0
+c_num_out_clks = 1
+c_clkout1_drives = BUFG
+c_clkout2_drives = BUFG
+c_clkout3_drives = BUFG
+c_clkout4_drives = BUFG
+c_clkout5_drives = BUFG
+c_clkout6_drives = BUFG
+c_clkout7_drives = BUFG
+c_inclk_sum_row0 = Input Clock Input Freq (MHz) Input Jitter (UI)
+c_inclk_sum_row1 = primary 26 0.010
+c_inclk_sum_row2 = no secondary input clock
+c_outclk_sum_row0a = Output Output Phase Duty Cycle Pk-to-Pk Phase
+c_outclk_sum_row0b = Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+c_outclk_sum_row1 = CLK_OUT1 74.287 0.000 N/A 200.000 N/A
+c_outclk_sum_row2 = no CLK_OUT2 output
+c_outclk_sum_row3 = no CLK_OUT3 output
+c_outclk_sum_row4 = no CLK_OUT4 output
+c_outclk_sum_row5 = no CLK_OUT5 output
+c_outclk_sum_row6 = no CLK_OUT6 output
+c_outclk_sum_row7 = no CLK_OUT7 output
+c_clkout1_requested_out_freq = 74.285
+c_clkout2_requested_out_freq = 100.000
+c_clkout3_requested_out_freq = 100.000
+c_clkout4_requested_out_freq = 100.000
+c_clkout5_requested_out_freq = 100.000
+c_clkout6_requested_out_freq = 100.000
+c_clkout7_requested_out_freq = 100.000
+c_clkout1_requested_phase = 0.000
+c_clkout2_requested_phase = 0.000
+c_clkout3_requested_phase = 0.000
+c_clkout4_requested_phase = 0.000
+c_clkout5_requested_phase = 0.000
+c_clkout6_requested_phase = 0.000
+c_clkout7_requested_phase = 0.000
+c_clkout1_requested_duty_cycle = 50.0
+c_clkout2_requested_duty_cycle = 50.0
+c_clkout3_requested_duty_cycle = 50.0
+c_clkout4_requested_duty_cycle = 50.0
+c_clkout5_requested_duty_cycle = 50.0
+c_clkout6_requested_duty_cycle = 50.0
+c_clkout7_requested_duty_cycle = 50.0
+c_clkout1_out_freq = 74.287
+c_clkout2_out_freq = N/A
+c_clkout3_out_freq = N/A
+c_clkout4_out_freq = N/A
+c_clkout5_out_freq = N/A
+c_clkout6_out_freq = N/A
+c_clkout7_out_freq = N/A
+c_clkout1_phase = 0.000
+c_clkout2_phase = N/A
+c_clkout3_phase = N/A
+c_clkout4_phase = N/A
+c_clkout5_phase = N/A
+c_clkout6_phase = N/A
+c_clkout7_phase = N/A
+c_clkout1_duty_cycle = N/A
+c_clkout2_duty_cycle = N/A
+c_clkout3_duty_cycle = N/A
+c_clkout4_duty_cycle = N/A
+c_clkout5_duty_cycle = N/A
+c_clkout6_duty_cycle = N/A
+c_clkout7_duty_cycle = N/A
+c_mmcm_notes = None
+c_mmcm_bandwidth = OPTIMIZED
+c_mmcm_clkfbout_mult_f = 4.000
+c_mmcm_clkin1_period = 10.000
+c_mmcm_clkin2_period = 10.000
+c_mmcm_clkout4_cascade = FALSE
+c_mmcm_clock_hold = FALSE
+c_mmcm_compensation = ZHOLD
+c_mmcm_divclk_divide = 1
+c_mmcm_ref_jitter1 = 0.010
+c_mmcm_ref_jitter2 = 0.010
+c_mmcm_startup_wait = FALSE
+c_mmcm_clkout0_divide_f = 4.000
+c_mmcm_clkout1_divide = 1
+c_mmcm_clkout2_divide = 1
+c_mmcm_clkout3_divide = 1
+c_mmcm_clkout4_divide = 1
+c_mmcm_clkout5_divide = 1
+c_mmcm_clkout6_divide = 1
+c_mmcm_clkout0_duty_cycle = 0.500
+c_mmcm_clkout1_duty_cycle = 0.500
+c_mmcm_clkout2_duty_cycle = 0.500
+c_mmcm_clkout3_duty_cycle = 0.500
+c_mmcm_clkout4_duty_cycle = 0.500
+c_mmcm_clkout5_duty_cycle = 0.500
+c_mmcm_clkout6_duty_cycle = 0.500
+c_mmcm_clkfbout_phase = 0.000
+c_mmcm_clkout0_phase = 0.000
+c_mmcm_clkout1_phase = 0.000
+c_mmcm_clkout2_phase = 0.000
+c_mmcm_clkout3_phase = 0.000
+c_mmcm_clkout4_phase = 0.000
+c_mmcm_clkout5_phase = 0.000
+c_mmcm_clkout6_phase = 0.000
+c_mmcm_clkfbout_use_fine_ps = FALSE
+c_mmcm_clkout0_use_fine_ps = FALSE
+c_mmcm_clkout1_use_fine_ps = FALSE
+c_mmcm_clkout2_use_fine_ps = FALSE
+c_mmcm_clkout3_use_fine_ps = FALSE
+c_mmcm_clkout4_use_fine_ps = FALSE
+c_mmcm_clkout5_use_fine_ps = FALSE
+c_mmcm_clkout6_use_fine_ps = FALSE
+c_pll_notes = None
+c_pll_bandwidth = OPTIMIZED
+c_pll_clk_feedback = CLKFBOUT
+c_pll_clkfbout_mult = 4
+c_pll_clkin_period = 10.000
+c_pll_compensation = INTERNAL
+c_pll_divclk_divide = 1
+c_pll_ref_jitter = 0.010
+c_pll_clkout0_divide = 1
+c_pll_clkout1_divide = 1
+c_pll_clkout2_divide = 1
+c_pll_clkout3_divide = 1
+c_pll_clkout4_divide = 1
+c_pll_clkout5_divide = 1
+c_pll_clkout0_duty_cycle = 0.500
+c_pll_clkout1_duty_cycle = 0.500
+c_pll_clkout2_duty_cycle = 0.500
+c_pll_clkout3_duty_cycle = 0.500
+c_pll_clkout4_duty_cycle = 0.500
+c_pll_clkout5_duty_cycle = 0.500
+c_pll_clkfbout_phase = 0.000
+c_pll_clkout0_phase = 0.000
+c_pll_clkout1_phase = 0.000
+c_pll_clkout2_phase = 0.000
+c_pll_clkout3_phase = 0.000
+c_pll_clkout4_phase = 0.000
+c_pll_clkout5_phase = 0.000
+c_dcm_notes = None
+c_dcm_clkdv_divide = 2.000
+c_dcm_clkfx_divide = 1
+c_dcm_clkfx_multiply = 4
+c_dcm_clkin_divide_by_2 = FALSE
+c_dcm_clkin_period = 10.000
+c_dcm_clkout_phase_shift = NONE
+c_dcm_clk_feedback = 1X
+c_dcm_clk_feedback_port = CLKOUT1
+c_dcm_deskew_adjust = SYSTEM_SYNCHRONOUS
+c_dcm_phase_shift = 0
+c_dcm_startup_wait = FALSE
+c_dcm_clk_out1_port = CLK0
+c_dcm_clk_out2_port = NONE
+c_dcm_clk_out3_port = NONE
+c_dcm_clk_out4_port = NONE
+c_dcm_clk_out5_port = NONE
+c_dcm_clk_out6_port = NONE
+c_dcm_clkgen_notes = 720p60hzclocksource
+c_dcm_clkgen_clkfxdv_divide = 2
+c_dcm_clkgen_clkfx_divide = 7
+c_dcm_clkgen_clkfx_multiply = 20
+c_dcm_clkgen_dfs_bandwidth = OPTIMIZED
+c_dcm_clkgen_prog_md_bandwidth = OPTIMIZED
+c_dcm_clkgen_clkin_period = 38.461
+c_dcm_clkgen_clkfx_md_max = 0.000
+c_dcm_clkgen_spread_spectrum = NONE
+c_dcm_clkgen_startup_wait = FALSE
+c_dcm_clkgen_clk_out1_port = CLKFX
+c_dcm_clkgen_clk_out2_port = NONE
+c_dcm_clkgen_clk_out3_port = NONE
+c_clock_mgr_type = MANUAL
+c_override_mmcm = 0
+c_override_pll = 0
+c_override_dcm = 0
+c_override_dcm_clkgen = 1
+c_dcm_pll_cascade = NONE
+c_primary_port = CLK_IN1
+c_secondary_port = CLK_IN2
+c_clk_out1_port = CLK_OUT1
+c_clk_out2_port = CLK_OUT2
+c_clk_out3_port = CLK_OUT3
+c_clk_out4_port = CLK_OUT4
+c_clk_out5_port = CLK_OUT5
+c_clk_out6_port = CLK_OUT6
+c_clk_out7_port = CLK_OUT7
+c_reset_port = RESET
+c_locked_port = LOCKED
+c_clkfb_in_port = CLKFB_IN
+c_clkfb_in_p_port = CLKFB_IN_P
+c_clkfb_in_n_port = CLKFB_IN_N
+c_clkfb_out_port = CLKFB_OUT
+c_clkfb_out_p_port = CLKFB_OUT_P
+c_clkfb_out_n_port = CLKFB_OUT_N
+c_power_down_port = POWER_DOWN
+c_daddr_port = DADDR
+c_dclk_port = DCLK
+c_drdy_port = DRDY
+c_dwe_port = DWE
+c_din_port = DIN
+c_dout_port = DOUT
+c_den_port = DEN
+c_psclk_port = PSCLK
+c_psen_port = PSEN
+c_psincdec_port = PSINCDEC
+c_psdone_port = PSDONE
+c_clk_valid_port = CLK_VALID
+c_status_port = STATUS
+c_clk_in_sel_port = CLK_IN_SEL
+c_input_clk_stopped_port = INPUT_CLK_STOPPED
+c_clkin1_jitter_ps = 384.61
+c_clkin2_jitter_ps = 100.0
+ComponentName = clkgendcm_720p60hz
diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.gise b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.gise new file mode 100755 index 0000000..885900b --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.gise @@ -0,0 +1,31 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="clkgendcm_720p60hz.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="clkgendcm_720p60hz.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="clkgendcm_720p60hz.veo" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v new file mode 100755 index 0000000..ba2ad2f --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v @@ -0,0 +1,133 @@ +// file: clkgendcm_720p60hz.v
+//
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// 720p60hzclocksource
+//
+//----------------------------------------------------------------------------
+// Output Output Phase Duty Cycle Pk-to-Pk Phase
+// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+//----------------------------------------------------------------------------
+// CLK_OUT1 74.287 0.000 N/A 200.000 N/A
+//
+//----------------------------------------------------------------------------
+// Input Clock Input Freq (MHz) Input Jitter (UI)
+//----------------------------------------------------------------------------
+// primary 26 0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "clkgendcm_720p60hz,clk_wiz_v3_1,{component_name=clkgendcm_720p60hz,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_CLKGEN,num_out_clk=1,clkin1_period=38.461,clkin2_period=38.461,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=true}" *)
+module clkgendcm_720p60hz
+ (// Clock in ports
+ input CLK_IN1,
+ // Clock out ports
+ output CLK_OUT1,
+ // Status and control signals
+ input RESET,
+ output LOCKED
+ );
+
+ // Input buffering
+ //------------------------------------
+ assign clkin1 = CLK_IN1;
+
+
+ // Clocking primitive
+ //------------------------------------
+ // Instantiation of the DCM primitive
+ // * Unused inputs are tied off
+ // * Unused outputs are labeled unused
+ wire psdone_unused;
+ wire locked_int;
+ wire [2:1] status_int;
+ wire clkfx;
+ wire clkfx180_unused;
+ wire clkfxdv_unused;
+
+ DCM_CLKGEN
+ #(.CLKFXDV_DIVIDE (2),
+ .CLKFX_DIVIDE (7),
+ .CLKFX_MULTIPLY (20),
+ .SPREAD_SPECTRUM ("NONE"),
+ .STARTUP_WAIT ("FALSE"),
+ .CLKIN_PERIOD (38.461),
+ .CLKFX_MD_MAX (2.8571))
+ dcm_clkgen_inst
+ // Input clock
+ (.CLKIN (clkin1),
+ // Output clocks
+ .CLKFX (clkfx),
+ .CLKFX180 (clkfx180_unused),
+ .CLKFXDV (clkfxdv_unused),
+ // Ports for dynamic reconfiguration
+ .PROGCLK (1'b0),
+ .PROGDATA (PROGDATA),
+ .PROGEN (PROGEN),
+ .PROGDONE (progdone_unused),
+ // Other control and status signals
+ .FREEZEDCM (1'b0),
+ .LOCKED (locked_int),
+ .STATUS (status_int),
+ .RST (RESET));
+
+ assign LOCKED = locked_int;
+
+ // Output buffering
+ //-----------------------------------
+
+ BUFG clkout1_buf
+ (.O (CLK_OUT1),
+ .I (clkfx));
+
+
+
+
+endmodule
diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.veo b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.veo new file mode 100755 index 0000000..ad61554 --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.veo @@ -0,0 +1,78 @@ +//
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// 720p60hzclocksource
+//
+//----------------------------------------------------------------------------
+// Output Output Phase Duty Cycle Pk-to-Pk Phase
+// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+//----------------------------------------------------------------------------
+// CLK_OUT1 74.287 0.000 N/A 200.000 N/A
+//
+//----------------------------------------------------------------------------
+// Input Clock Input Freq (MHz) Input Jitter (UI)
+//----------------------------------------------------------------------------
+// primary 26 0.010
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+ clkgendcm_720p60hz instance_name
+ (// Clock in ports
+ .CLK_IN1(CLK_IN1), // IN
+ // Clock out ports
+ .CLK_OUT1(CLK_OUT1), // OUT
+ // Status and control signals
+ .RESET(RESET),// IN
+ .LOCKED(LOCKED)); // OUT
+// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v~ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v~ new file mode 100755 index 0000000..d6fa44b --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.v~ @@ -0,0 +1,133 @@ +// file: clkgendcm_720p60hz.v
+//
+// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// 720p60hzclocksource
+//
+//----------------------------------------------------------------------------
+// Output Output Phase Duty Cycle Pk-to-Pk Phase
+// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+//----------------------------------------------------------------------------
+// CLK_OUT1 74.287 0.000 N/A 200.000 N/A
+//
+//----------------------------------------------------------------------------
+// Input Clock Input Freq (MHz) Input Jitter (UI)
+//----------------------------------------------------------------------------
+// primary 26 0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "clkgendcm_720p60hz,clk_wiz_v3_1,{component_name=clkgendcm_720p60hz,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_CLKGEN,num_out_clk=1,clkin1_period=38.461,clkin2_period=38.461,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=true}" *)
+module clkgendcm_720p60hz
+ (// Clock in ports
+ input CLK_IN1,
+ // Clock out ports
+ output CLK_OUT1,
+ // Status and control signals
+ input RESET,
+ output LOCKED
+ );
+
+ // Input buffering
+ //------------------------------------
+ assign clkin1 = CLK_IN1;
+
+
+ // Clocking primitive
+ //------------------------------------
+ // Instantiation of the DCM primitive
+ // * Unused inputs are tied off
+ // * Unused outputs are labeled unused
+ wire psdone_unused;
+ wire locked_int;
+ wire [2:1] status_int;
+ wire clkfx;
+ wire clkfx180_unused;
+ wire clkfxdv_unused;
+
+ DCM_CLKGEN
+ #(.CLKFXDV_DIVIDE (2),
+ .CLKFX_DIVIDE (7),
+ .CLKFX_MULTIPLY (20),
+ .SPREAD_SPECTRUM ("NONE"),
+ .STARTUP_WAIT ("FALSE"),
+ .CLKIN_PERIOD (38.461),
+ .CLKFX_MD_MAX (0.000))
+ dcm_clkgen_inst
+ // Input clock
+ (.CLKIN (clkin1),
+ // Output clocks
+ .CLKFX (clkfx),
+ .CLKFX180 (clkfx180_unused),
+ .CLKFXDV (clkfxdv_unused),
+ // Ports for dynamic reconfiguration
+ .PROGCLK (1'b0),
+ .PROGDATA (PROGDATA),
+ .PROGEN (PROGEN),
+ .PROGDONE (progdone_unused),
+ // Other control and status signals
+ .FREEZEDCM (1'b0),
+ .LOCKED (locked_int),
+ .STATUS (status_int),
+ .RST (RESET));
+
+ assign LOCKED = locked_int;
+
+ // Output buffering
+ //-----------------------------------
+
+ BUFG clkout1_buf
+ (.O (CLK_OUT1),
+ .I (clkfx));
+
+
+
+
+endmodule
diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xco b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xco new file mode 100755 index 0000000..5d38e7f --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xco @@ -0,0 +1,256 @@ +##############################################################
+#
+# Xilinx Core Generator version 13.1
+# Date: Tue Aug 09 21:40:17 2011
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Clocking_Wizard family Xilinx,_Inc. 3.1
+# END Select
+# BEGIN Parameters
+CSET calc_done=DONE
+CSET clk_in_sel_port=CLK_IN_SEL
+CSET clk_out1_port=CLK_OUT1
+CSET clk_out1_use_fine_ps_gui=false
+CSET clk_out2_port=CLK_OUT2
+CSET clk_out2_use_fine_ps_gui=false
+CSET clk_out3_port=CLK_OUT3
+CSET clk_out3_use_fine_ps_gui=false
+CSET clk_out4_port=CLK_OUT4
+CSET clk_out4_use_fine_ps_gui=false
+CSET clk_out5_port=CLK_OUT5
+CSET clk_out5_use_fine_ps_gui=false
+CSET clk_out6_port=CLK_OUT6
+CSET clk_out6_use_fine_ps_gui=false
+CSET clk_out7_port=CLK_OUT7
+CSET clk_out7_use_fine_ps_gui=false
+CSET clk_valid_port=CLK_VALID
+CSET clkfb_in_n_port=CLKFB_IN_N
+CSET clkfb_in_p_port=CLKFB_IN_P
+CSET clkfb_in_port=CLKFB_IN
+CSET clkfb_in_signaling=SINGLE
+CSET clkfb_out_n_port=CLKFB_OUT_N
+CSET clkfb_out_p_port=CLKFB_OUT_P
+CSET clkfb_out_port=CLKFB_OUT
+CSET clkin1_jitter_ps=384.61
+CSET clkin1_ui_jitter=0.010
+CSET clkin2_jitter_ps=100.0
+CSET clkin2_ui_jitter=0.010
+CSET clkout1_drives=BUFG
+CSET clkout1_requested_duty_cycle=50.0
+CSET clkout1_requested_out_freq=74.285
+CSET clkout1_requested_phase=0.000
+CSET clkout2_drives=BUFG
+CSET clkout2_requested_duty_cycle=50.0
+CSET clkout2_requested_out_freq=100.000
+CSET clkout2_requested_phase=0.000
+CSET clkout2_used=false
+CSET clkout3_drives=BUFG
+CSET clkout3_requested_duty_cycle=50.0
+CSET clkout3_requested_out_freq=100.000
+CSET clkout3_requested_phase=0.000
+CSET clkout3_used=false
+CSET clkout4_drives=BUFG
+CSET clkout4_requested_duty_cycle=50.0
+CSET clkout4_requested_out_freq=100.000
+CSET clkout4_requested_phase=0.000
+CSET clkout4_used=false
+CSET clkout5_drives=BUFG
+CSET clkout5_requested_duty_cycle=50.0
+CSET clkout5_requested_out_freq=100.000
+CSET clkout5_requested_phase=0.000
+CSET clkout5_used=false
+CSET clkout6_drives=BUFG
+CSET clkout6_requested_duty_cycle=50.0
+CSET clkout6_requested_out_freq=100.000
+CSET clkout6_requested_phase=0.000
+CSET clkout6_used=false
+CSET clkout7_drives=BUFG
+CSET clkout7_requested_duty_cycle=50.0
+CSET clkout7_requested_out_freq=100.000
+CSET clkout7_requested_phase=0.000
+CSET clkout7_used=false
+CSET clock_mgr_type=MANUAL
+CSET component_name=clkgendcm_720p60hz
+CSET daddr_port=DADDR
+CSET dclk_port=DCLK
+CSET dcm_clk_feedback=1X
+CSET dcm_clk_out1_port=CLK0
+CSET dcm_clk_out2_port=CLK0
+CSET dcm_clk_out3_port=CLK0
+CSET dcm_clk_out4_port=CLK0
+CSET dcm_clk_out5_port=CLK0
+CSET dcm_clk_out6_port=CLK0
+CSET dcm_clkdv_divide=2.0
+CSET dcm_clkfx_divide=1
+CSET dcm_clkfx_multiply=4
+CSET dcm_clkgen_clk_out1_port=CLKFX
+CSET dcm_clkgen_clk_out2_port=CLKFX
+CSET dcm_clkgen_clk_out3_port=CLKFX
+CSET dcm_clkgen_clkfx_divide=7
+CSET dcm_clkgen_clkfx_md_max=0
+CSET dcm_clkgen_clkfx_multiply=20
+CSET dcm_clkgen_clkfxdv_divide=2
+CSET dcm_clkgen_clkin_period=38.461
+CSET dcm_clkgen_notes=720p60hzclocksource
+CSET dcm_clkgen_spread_spectrum=NONE
+CSET dcm_clkgen_startup_wait=false
+CSET dcm_clkin_divide_by_2=false
+CSET dcm_clkin_period=10.000
+CSET dcm_clkout_phase_shift=NONE
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
+CSET dcm_notes=None
+CSET dcm_phase_shift=0
+CSET dcm_pll_cascade=NONE
+CSET dcm_startup_wait=false
+CSET den_port=DEN
+CSET din_port=DIN
+CSET dout_port=DOUT
+CSET drdy_port=DRDY
+CSET dwe_port=DWE
+CSET feedback_source=FDBK_AUTO
+CSET in_freq_units=Units_MHz
+CSET in_jitter_units=Units_UI
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED
+CSET jitter_options=UI
+CSET jitter_sel=No_Jitter
+CSET locked_port=LOCKED
+CSET mmcm_bandwidth=OPTIMIZED
+CSET mmcm_clkfbout_mult_f=4.000
+CSET mmcm_clkfbout_phase=0.000
+CSET mmcm_clkfbout_use_fine_ps=false
+CSET mmcm_clkin1_period=10.000
+CSET mmcm_clkin2_period=10.000
+CSET mmcm_clkout0_divide_f=4.000
+CSET mmcm_clkout0_duty_cycle=0.500
+CSET mmcm_clkout0_phase=0.000
+CSET mmcm_clkout0_use_fine_ps=false
+CSET mmcm_clkout1_divide=1
+CSET mmcm_clkout1_duty_cycle=0.500
+CSET mmcm_clkout1_phase=0.000
+CSET mmcm_clkout1_use_fine_ps=false
+CSET mmcm_clkout2_divide=1
+CSET mmcm_clkout2_duty_cycle=0.500
+CSET mmcm_clkout2_phase=0.000
+CSET mmcm_clkout2_use_fine_ps=false
+CSET mmcm_clkout3_divide=1
+CSET mmcm_clkout3_duty_cycle=0.500
+CSET mmcm_clkout3_phase=0.000
+CSET mmcm_clkout3_use_fine_ps=false
+CSET mmcm_clkout4_cascade=false
+CSET mmcm_clkout4_divide=1
+CSET mmcm_clkout4_duty_cycle=0.500
+CSET mmcm_clkout4_phase=0.000
+CSET mmcm_clkout4_use_fine_ps=false
+CSET mmcm_clkout5_divide=1
+CSET mmcm_clkout5_duty_cycle=0.500
+CSET mmcm_clkout5_phase=0.000
+CSET mmcm_clkout5_use_fine_ps=false
+CSET mmcm_clkout6_divide=1
+CSET mmcm_clkout6_duty_cycle=0.500
+CSET mmcm_clkout6_phase=0.000
+CSET mmcm_clkout6_use_fine_ps=false
+CSET mmcm_clock_hold=false
+CSET mmcm_compensation=ZHOLD
+CSET mmcm_divclk_divide=1
+CSET mmcm_notes=None
+CSET mmcm_ref_jitter1=0.010
+CSET mmcm_ref_jitter2=0.010
+CSET mmcm_startup_wait=false
+CSET num_out_clks=1
+CSET override_dcm=false
+CSET override_dcm_clkgen=true
+CSET override_mmcm=false
+CSET override_pll=false
+CSET platform=nt64
+CSET pll_bandwidth=OPTIMIZED
+CSET pll_clk_feedback=CLKFBOUT
+CSET pll_clkfbout_mult=4
+CSET pll_clkfbout_phase=0.000
+CSET pll_clkin_period=10.000
+CSET pll_clkout0_divide=1
+CSET pll_clkout0_duty_cycle=0.500
+CSET pll_clkout0_phase=0.000
+CSET pll_clkout1_divide=1
+CSET pll_clkout1_duty_cycle=0.500
+CSET pll_clkout1_phase=0.000
+CSET pll_clkout2_divide=1
+CSET pll_clkout2_duty_cycle=0.500
+CSET pll_clkout2_phase=0.000
+CSET pll_clkout3_divide=1
+CSET pll_clkout3_duty_cycle=0.500
+CSET pll_clkout3_phase=0.000
+CSET pll_clkout4_divide=1
+CSET pll_clkout4_duty_cycle=0.500
+CSET pll_clkout4_phase=0.000
+CSET pll_clkout5_divide=1
+CSET pll_clkout5_duty_cycle=0.500
+CSET pll_clkout5_phase=0.000
+CSET pll_compensation=INTERNAL
+CSET pll_divclk_divide=1
+CSET pll_notes=None
+CSET pll_ref_jitter=0.010
+CSET power_down_port=POWER_DOWN
+CSET prim_in_freq=26
+CSET prim_in_jitter=0.010
+CSET prim_source=No_buffer
+CSET primary_port=CLK_IN1
+CSET primtype_sel=DCM_CLKGEN
+CSET psclk_port=PSCLK
+CSET psdone_port=PSDONE
+CSET psen_port=PSEN
+CSET psincdec_port=PSINCDEC
+CSET relative_inclk=REL_PRIMARY
+CSET reset_port=RESET
+CSET secondary_in_freq=100.000
+CSET secondary_in_jitter=0.010
+CSET secondary_port=CLK_IN2
+CSET secondary_source=Single_ended_clock_capable_pin
+CSET status_port=STATUS
+CSET summary_strings=empty
+CSET use_clk_valid=false
+CSET use_dyn_phase_shift=false
+CSET use_dyn_reconfig=false
+CSET use_freeze=false
+CSET use_freq_synth=true
+CSET use_inclk_stopped=false
+CSET use_inclk_switchover=false
+CSET use_locked=true
+CSET use_max_i_jitter=false
+CSET use_min_o_jitter=false
+CSET use_min_power=false
+CSET use_phase_alignment=false
+CSET use_power_down=false
+CSET use_reset=true
+CSET use_spread_spectrum=false
+CSET use_status=false
+# END Parameters
+GENERATE
+# CRC: fcd26fcc
diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xise b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xise new file mode 100755 index 0000000..38cc24b --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.xise @@ -0,0 +1,405 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="clkgendcm_720p60hz/clkgendcm_720p60hz.ucf" xil_pn:type="FILE_UCF"> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="clkgendcm_720p60hz/example_design/clkgendcm_720p60hz_exdes.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/> + </file> + <file xil_pn:name="clkgendcm_720p60hz.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="Implementation" xil_pn:seqID="4"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/> + </file> + </files> + + <properties> + <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> + <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> + <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> + <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/> + <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/> + <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/> + <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/> + <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property 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xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/> + <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> + <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> + <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> + <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/> + <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> + <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> + <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> + <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> + <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/> + <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> + <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/> + <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> + <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> + <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> + <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> + <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/> + <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_DesignName" xil_pn:value="clkgendcm_720p60hz" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-08-10T05:40:25" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="49F77439300843CA94ECE35E731FBF66" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_flist.txt b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_flist.txt new file mode 100755 index 0000000..2a77c03 --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_flist.txt @@ -0,0 +1,33 @@ +# Output products list for <clkgendcm_720p60hz>
+clkgendcm_720p60hz\clk_wiz_readme.txt
+clkgendcm_720p60hz\clkgendcm_720p60hz.ucf
+clkgendcm_720p60hz\doc\clk_wiz_ds709.pdf
+clkgendcm_720p60hz\doc\clk_wiz_gsg521.pdf
+clkgendcm_720p60hz\example_design\clkgendcm_720p60hz_exdes.v
+clkgendcm_720p60hz\implement\implement.bat
+clkgendcm_720p60hz\implement\implement.sh
+clkgendcm_720p60hz\implement\planAhead_ise.bat
+clkgendcm_720p60hz\implement\planAhead_ise.sh
+clkgendcm_720p60hz\implement\planAhead_ise.tcl
+clkgendcm_720p60hz\implement\xst.prj
+clkgendcm_720p60hz\implement\xst.scr
+clkgendcm_720p60hz\simulation\clkgendcm_720p60hz_tb.v
+clkgendcm_720p60hz\simulation\functional\simcmds.tcl
+clkgendcm_720p60hz\simulation\functional\simulate_isim.bat
+clkgendcm_720p60hz\simulation\functional\simulate_isim.sh
+clkgendcm_720p60hz\simulation\functional\simulate_mti.do
+clkgendcm_720p60hz\simulation\functional\simulate_ncsim.sh
+clkgendcm_720p60hz\simulation\functional\simulate_vcs.sh
+clkgendcm_720p60hz\simulation\functional\ucli_commands.key
+clkgendcm_720p60hz\simulation\functional\vcs_session.tcl
+clkgendcm_720p60hz\simulation\functional\wave.do
+clkgendcm_720p60hz\simulation\functional\wave.sv
+clkgendcm_720p60hz.asy
+clkgendcm_720p60hz.ejp
+clkgendcm_720p60hz.gise
+clkgendcm_720p60hz.v
+clkgendcm_720p60hz.veo
+clkgendcm_720p60hz.xco
+clkgendcm_720p60hz.xise
+clkgendcm_720p60hz_flist.txt
+clkgendcm_720p60hz_xmdf.tcl
diff --git a/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_xmdf.tcl b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_xmdf.tcl new file mode 100755 index 0000000..6001376 --- /dev/null +++ b/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz_xmdf.tcl @@ -0,0 +1,144 @@ +# The package naming convention is <core_name>_xmdf
+package provide clkgendcm_720p60hz_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::clkgendcm_720p60hz_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::clkgendcm_720p60hz_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name clkgendcm_720p60hz
+}
+# ::clkgendcm_720p60hz_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::clkgendcm_720p60hz_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/clk_wiz_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/clkgendcm_720p60hz.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/doc/clk_wiz_ds709.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/doc/clk_wiz_gsg521.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/example_design/clkgendcm_720p60hz_exdes.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/clkgendcm_720p60hz_tb.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/simcmds.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/simulate_isim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/simulate_vcs.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/ucli_commands.key
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/vcs_session.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/wave.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz/simulation/functional/wave.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz.ejp
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path clkgendcm_720p60hz_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module clkgendcm_720p60hz
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/ip/clk_wiz_v3_1_0/coregen.cgc b/ip/clk_wiz_v3_1_0/coregen.cgc new file mode 100755 index 0000000..0e18e96 --- /dev/null +++ b/ip/clk_wiz_v3_1_0/coregen.cgc @@ -0,0 +1,860 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" >
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>projects</spirit:library>
+ <spirit:name>coregen</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>clkgendcm_720p60hz</spirit:instanceName>
+ <spirit:description>Generated by PlanAhead</spirit:description>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="3.1" />
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">clkgendcm_720p60hz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">PSEN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFX_DIVIDE">7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKIN_PERIOD">38.461</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">LOCKED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">CLK_IN_SEL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLK_OUT1_PORT">CLKFX</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_DCM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFX_MULTIPLY">20</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">74.285</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLK_OUT2_PORT">CLKFX</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">INPUT_CLK_STOPPED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLK_OUT3_PORT">CLKFX</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFX_MD_MAX">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">26</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">CLKFB_OUT_N</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_PHASE_SHIFT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">PSINCDEC</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">DRDY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">DIN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">CLKFB_OUT_P</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">CLKFB_IN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">DWE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_DCM_CLKGEN">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">RESET</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">CLK_IN2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">PSDONE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT1_PORT">CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">DOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT2_PORT">CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_CLKFXDV_DIVIDE">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT3_PORT">CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">DADDR</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">POWER_DOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">CLKFB_OUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_FEEDBACK">1X</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">384.61</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT4_PORT">CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">4.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">DONE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT5_PORT">CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLK_OUT6_PORT">CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">CLK_OUT1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_PLL_CASCADE">NONE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">PSCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">DCLK</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">INTERNAL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">CLKFB_IN_N</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">CLK_OUT2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">DEN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">MANUAL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">CLK_OUT3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">CLKFB_IN_P</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_DESKEW_ADJUST">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKFX_MULTIPLY">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">CLK_OUT4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKDV_DIVIDE">2.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKFX_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">CLK_OUT5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">CLK_OUT6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">CLK_OUT7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKOUT_PHASE_SHIFT">NONE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKIN_DIVIDE_BY_2">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">4.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_SPREAD_SPECTRUM">NONE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">nt64</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCM_CLKGEN_NOTES">720p60hzclocksource</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">DCM_CLKGEN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">CLK_IN1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">DCM_CLKGEN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">PSDONE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">CLK_IN1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKFX_MULTIPLY">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">74.287</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">CLK_OUT1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">MANUAL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">CLK_OUT2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_DCM_CLKGEN">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">CLK_OUT3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">CLK_OUT4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKGEN_CLKFXDV_DIVIDE">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_DCM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">CLK_OUT5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">4.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">CLK_OUT6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">CLK_OUT7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">DEN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">PSEN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">CLKFB_OUT_N</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">26</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">CLK_IN_SEL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKOUT_PHASE_SHIFT">NONE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Input Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">primary 26 0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no secondary input clock </spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">CLKFB_OUT_P</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKGEN_CLK_OUT1_PORT">CLKFX</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKGEN_CLK_OUT2_PORT">NONE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKGEN_CLK_OUT3_PORT">NONE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_PHASE_SHIFT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKIN_DIVIDE_BY_2">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">DRDY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">nt64</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLK_FEEDBACK">1X</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">384.61</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">4.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKGEN_SPREAD_SPECTRUM">NONE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKGEN_CLKFX_DIVIDE">7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKGEN_CLKIN_PERIOD">38.461</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">INPUT_CLK_STOPPED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">INTERNAL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKGEN_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLK_FEEDBACK_PORT">CLKOUT1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLK_OUT1_PORT">CLK0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">LOCKED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">DOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">POWER_DOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">RESET</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLK_OUT2_PORT">NONE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1 74.287 0.000 N/A 200.000 N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">no CLK_OUT2 output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no CLK_OUT3 output </spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">PSINCDEC</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no CLK_OUT4 output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKGEN_CLKFX_MD_MAX">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLKDV_DIVIDE">2.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no CLK_OUT5 output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCM_CLK_OUT3_PORT">NONE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no CLK_OUT6 output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no CLK_OUT7 output </spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">N/A</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
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+ <xilinx:timeStamp>Tue Aug 09 21:40:17 GMT 2011</xilinx:timeStamp>
+ <xilinx:checkSum>0x59A939F4</xilinx:checkSum>
+ <xilinx:generationId>generationid_1508053363</xilinx:generationId>
+ </xilinx:file>
+ <xilinx:file>
+ <xilinx:name>./clkgendcm_720p60hz_xmdf.tcl</xilinx:name>
+ <xilinx:userFileType>tcl</xilinx:userFileType>
+ <xilinx:timeStamp>Tue Aug 09 21:40:18 GMT 2011</xilinx:timeStamp>
+ <xilinx:checkSum>0x2BF520E1</xilinx:checkSum>
+ <xilinx:generationId>generationid_1508053363</xilinx:generationId>
+ </xilinx:file>
+ </xilinx:fileSet>
+ <xilinx:fileSet>
+ <xilinx:name>instantiation_template_generator</xilinx:name>
+ <xilinx:file>
+ <xilinx:name>./clkgendcm_720p60hz.veo</xilinx:name>
+ <xilinx:userFileType>veo</xilinx:userFileType>
+ <xilinx:timeStamp>Tue Aug 09 21:40:20 GMT 2011</xilinx:timeStamp>
+ <xilinx:checkSum>0x59A939F4</xilinx:checkSum>
+ <xilinx:generationId>generationid_1508053363</xilinx:generationId>
+ </xilinx:file>
+ </xilinx:fileSet>
+ <xilinx:fileSet>
+ <xilinx:name>asy_generator</xilinx:name>
+ <xilinx:file>
+ <xilinx:name>./clkgendcm_720p60hz.asy</xilinx:name>
+ <xilinx:userFileType>asy</xilinx:userFileType>
+ <xilinx:timeStamp>Tue Aug 09 21:40:24 GMT 2011</xilinx:timeStamp>
+ <xilinx:checkSum>0x4709598E</xilinx:checkSum>
+ <xilinx:generationId>generationid_1508053363</xilinx:generationId>
+ </xilinx:file>
+ </xilinx:fileSet>
+ <xilinx:fileSet>
+ <xilinx:name>xmdf_generator</xilinx:name>
+ </xilinx:fileSet>
+ <xilinx:fileSet>
+ <xilinx:name>ise_generator</xilinx:name>
+ <xilinx:file>
+ <xilinx:name>./clkgendcm_720p60hz.gise</xilinx:name>
+ <xilinx:userFileType>ignore</xilinx:userFileType>
+ <xilinx:userFileType>gise</xilinx:userFileType>
+ <xilinx:timeStamp>Tue Aug 09 21:40:26 GMT 2011</xilinx:timeStamp>
+ <xilinx:checkSum>0x62A4AF22</xilinx:checkSum>
+ <xilinx:generationId>generationid_1508053363</xilinx:generationId>
+ </xilinx:file>
+ <xilinx:file>
+ <xilinx:name>./clkgendcm_720p60hz.xise</xilinx:name>
+ <xilinx:userFileType>ignore</xilinx:userFileType>
+ <xilinx:userFileType>xise</xilinx:userFileType>
+ <xilinx:timeStamp>Tue Aug 09 21:40:26 GMT 2011</xilinx:timeStamp>
+ <xilinx:checkSum>0x23EDC58D</xilinx:checkSum>
+ <xilinx:generationId>generationid_1508053363</xilinx:generationId>
+ </xilinx:file>
+ </xilinx:fileSet>
+ <xilinx:fileSet>
+ <xilinx:name>deliver_readme_generator</xilinx:name>
+ </xilinx:fileSet>
+ <xilinx:fileSet>
+ <xilinx:name>flist_generator</xilinx:name>
+ <xilinx:file>
+ <xilinx:name>./clkgendcm_720p60hz_flist.txt</xilinx:name>
+ <xilinx:userFileType>ignore</xilinx:userFileType>
+ <xilinx:userFileType>txtFlist</xilinx:userFileType>
+ <xilinx:userFileType>txt</xilinx:userFileType>
+ <xilinx:timeStamp>Tue Aug 09 21:40:26 GMT 2011</xilinx:timeStamp>
+ <xilinx:checkSum>0xC1C72AE1</xilinx:checkSum>
+ <xilinx:generationId>generationid_1508053363</xilinx:generationId>
+ </xilinx:file>
+ </xilinx:fileSet>
+ </xilinx:generationHistory>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ <spirit:componentInstance>
+ <spirit:instanceName>clk_wiz_v3_1_0</spirit:instanceName>
+ <spirit:description>Generated by PlanAhead</spirit:description>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="3.1" />
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">clk_wiz_v3_1_0</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:instanceProperties xmlns:xilinx="http://www.xilinx.com">
+ <xilinx:projectOptions>
+ <xilinx:projectName>coregen</xilinx:projectName>
+ <xilinx:outputDirectory>./</xilinx:outputDirectory>
+ <xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
+ <xilinx:subWorkingDirectory>./tmp/_cg</xilinx:subWorkingDirectory>
+ </xilinx:projectOptions>
+ <xilinx:part>
+ <xilinx:device>xc6slx9</xilinx:device>
+ <xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
+ <xilinx:package>tqg144</xilinx:package>
+ <xilinx:speedGrade>-2</xilinx:speedGrade>
+ </xilinx:part>
+ <xilinx:flowOptions>
+ <xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
+ <xilinx:designEntry>Verilog</xilinx:designEntry>
+ <xilinx:asySymbol>true</xilinx:asySymbol>
+ <xilinx:flowVendor>Other</xilinx:flowVendor>
+ <xilinx:addPads>false</xilinx:addPads>
+ <xilinx:removeRPMs>false</xilinx:removeRPMs>
+ <xilinx:createNDF>false</xilinx:createNDF>
+ <xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
+ <xilinx:formalVerification>false</xilinx:formalVerification>
+ </xilinx:flowOptions>
+ <xilinx:simulationOptions>
+ <xilinx:simulationModel>Behavioral</xilinx:simulationModel>
+ <xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
+ <xilinx:foundationSym>false</xilinx:foundationSym>
+ </xilinx:simulationOptions>
+ </xilinx:instanceProperties>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+ <spirit:vendorExtensions>
+ <xilinx:instanceProperties>
+ <xilinx:projectOptions>
+ <xilinx:projectName>coregen</xilinx:projectName>
+ <xilinx:outputDirectory>./</xilinx:outputDirectory>
+ <xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
+ <xilinx:subWorkingDirectory>./tmp/_cg</xilinx:subWorkingDirectory>
+ </xilinx:projectOptions>
+ <xilinx:part>
+ <xilinx:device>xc6slx9</xilinx:device>
+ <xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
+ <xilinx:package>tqg144</xilinx:package>
+ <xilinx:speedGrade>-2</xilinx:speedGrade>
+ </xilinx:part>
+ <xilinx:flowOptions>
+ <xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
+ <xilinx:designEntry>Verilog</xilinx:designEntry>
+ <xilinx:asySymbol>true</xilinx:asySymbol>
+ <xilinx:flowVendor>Other</xilinx:flowVendor>
+ <xilinx:addPads>false</xilinx:addPads>
+ <xilinx:removeRPMs>false</xilinx:removeRPMs>
+ <xilinx:createNDF>false</xilinx:createNDF>
+ <xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
+ <xilinx:formalVerification>false</xilinx:formalVerification>
+ </xilinx:flowOptions>
+ <xilinx:simulationOptions>
+ <xilinx:simulationModel>Behavioral</xilinx:simulationModel>
+ <xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
+ <xilinx:foundationSym>false</xilinx:foundationSym>
+ </xilinx:simulationOptions>
+ </xilinx:instanceProperties>
+ </spirit:vendorExtensions>
+</spirit:design>
diff --git a/ip/clk_wiz_v3_1_0/coregen.cgp b/ip/clk_wiz_v3_1_0/coregen.cgp new file mode 100755 index 0000000..555710a --- /dev/null +++ b/ip/clk_wiz_v3_1_0/coregen.cgp @@ -0,0 +1,22 @@ +# Date: Tue Aug 09 21:35:33 2011 +
+SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +SET workingdirectory = ./tmp/ +
+# CRC: e7d90245
diff --git a/ip/clk_wiz_v3_1_0/coregen.log b/ip/clk_wiz_v3_1_0/coregen.log new file mode 100755 index 0000000..f93187b --- /dev/null +++ b/ip/clk_wiz_v3_1_0/coregen.log @@ -0,0 +1,42 @@ +CoreGen has not been configured with any user repositories. +CoreGen has been configured with the following Xilinx repositories: + - 'C:\Xilinx\13.1\ISE_DS\ISE\coregen\' [] +INFO:sim:927 - Generating component instance 'clkgendcm_720p60hz' of
+ 'xilinx.com:ip:clk_wiz:3.1' from
+ 'C:\Xilinx\13.1\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3
+ _1\clk_wiz_v3_1.xcd'. +Resolving generic values... +Initializing IP model... +Loading device for application Rf_Device from file '6slx9.nph' in environment
+C:\Xilinx\13.1\ISE_DS\ISE\. +Finished initializing IP model. +Finished resolving generic values. +Generating IP... +WARNING:sim:89 - A core named <clkgendcm_720p60hz> already exists in the output
+ directory. Output products for this core may be overwritten. +Skipping VHDL instantiation template for clkgendcm_720p60hz... +Creating ISE instantiation template for clkgendcm_720p60hz... +Collating core files for clkgendcm_720p60hz +Collating core files for clkgendcm_720p60hz +Configuring files for clkgendcm_720p60hz root... +Finished Generation. +Generating IP instantiation template... +Finished generating IP instantiation template. +Generating ASY schematic symbol... +Initializing IP model... +Finished initializing IP model. +Finished generating ASY schematic symbol. +Generating metadata file... +Finished generating metadata file. +Generating ISE project... +WARNING:sim - This core does not have a top level called "/clkgendcm_720p60hz" +WARNING:sim - Top level has been set to "/clkgendcm_720p60hz_exdes" +Finished generating ISE project.Generating README file... +Finished generating README file. +Generating FLIST file... +Finished FLIST file generation. +Preparing output directory... +Finished preparing output directory. +Moving files to output directory... +Finished moving files to output directory +Saved options for project 'coregen'. diff --git a/ip/clk_wiz_v3_1_0/pa_cg_bom.xml b/ip/clk_wiz_v3_1_0/pa_cg_bom.xml new file mode 100755 index 0000000..7a61bc9 --- /dev/null +++ b/ip/clk_wiz_v3_1_0/pa_cg_bom.xml @@ -0,0 +1,61 @@ +<?xml version="1.0"?>
+<BillOfMaterials Version="1" Minor="2">
+ <IPInstance name="clkgendcm_720p60hz">
+ <FileSets>
+ <FileSet generator="model_parameter_resolution_generator">
+ <File name="./model_parameter_resolution_generator.xlog" type="ignore" timestamp="Tue Aug 09 21:40:26 GMT 2011" checksum="0xFFFFFFFF"></File>
+ </FileSet>
+ <FileSet generator="ip_xco_generator">
+ <File name="./clkgendcm_720p60hz.xco" type="xco" timestamp="Tue Aug 09 21:40:17 GMT 2011" checksum="0x920E017E"></File>
+ </FileSet>
+ <FileSet generator="ngc_netlist_generator">
+ <File name="./clkgendcm_720p60hz/clk_wiz_readme.txt" type="ignore" timestamp="Thu Feb 03 22:20:48 GMT 2011" checksum="0x63183E2A"></File>
+ <File name="./clkgendcm_720p60hz/clkgendcm_720p60hz.ucf" type="ucf" timestamp="Tue Aug 09 21:40:20 GMT 2011" checksum="0x5EC3B764"></File>
+ <File name="./clkgendcm_720p60hz/doc/clk_wiz_ds709.pdf" type="ignore" timestamp="Thu Feb 03 22:20:48 GMT 2011" checksum="0xC01920CC"></File>
+ <File name="./clkgendcm_720p60hz/doc/clk_wiz_gsg521.pdf" type="ignore" timestamp="Thu Feb 03 22:20:48 GMT 2011" checksum="0xBA196AB0"></File>
+ <File name="./clkgendcm_720p60hz/example_design/clkgendcm_720p60hz_exdes.v" type="verilog" timestamp="Tue Aug 09 21:40:17 GMT 2011" checksum="0x53DD6918"></File>
+ <File name="./clkgendcm_720p60hz/implement/implement.bat" type="ignore" timestamp="Tue Aug 09 21:40:20 GMT 2011" checksum="0x98AE950F"></File>
+ <File name="./clkgendcm_720p60hz/implement/implement.sh" type="ignore" timestamp="Tue Aug 09 21:40:19 GMT 2011" checksum="0xD7364919"></File>
+ <File name="./clkgendcm_720p60hz/implement/planAhead_ise.bat" type="ignore" timestamp="Tue Aug 09 21:40:19 GMT 2011" checksum="0x2D87B27F"></File>
+ <File name="./clkgendcm_720p60hz/implement/planAhead_ise.sh" type="ignore" timestamp="Tue Aug 09 21:40:19 GMT 2011" checksum="0x26D9E0AC"></File>
+ <File name="./clkgendcm_720p60hz/implement/planAhead_ise.tcl" type="ignore" timestamp="Tue Aug 09 21:40:19 GMT 2011" checksum="0xEE5C7326"></File>
+ <File name="./clkgendcm_720p60hz/implement/xst.prj" type="ignore" timestamp="Tue Aug 09 21:40:20 GMT 2011" checksum="0x3E535B2C"></File>
+ <File name="./clkgendcm_720p60hz/implement/xst.scr" type="ignore" timestamp="Tue Aug 09 21:40:20 GMT 2011" checksum="0x392E1A17"></File>
+ <File name="./clkgendcm_720p60hz/simulation/clkgendcm_720p60hz_tb.v" type="ignore" timestamp="Tue Aug 09 21:40:17 GMT 2011" checksum="0xE300FED0"></File>
+ <File name="./clkgendcm_720p60hz/simulation/functional/simcmds.tcl" type="ignore" timestamp="Tue Aug 09 21:40:19 GMT 2011" checksum="0x522C4A54"></File>
+ <File name="./clkgendcm_720p60hz/simulation/functional/simulate_isim.bat" type="ignore" timestamp="Tue Aug 09 21:40:18 GMT 2011" checksum="0x16B072E8"></File>
+ <File name="./clkgendcm_720p60hz/simulation/functional/simulate_isim.sh" type="ignore" timestamp="Tue Aug 09 21:40:19 GMT 2011" checksum="0x6A4E1E9B"></File>
+ <File name="./clkgendcm_720p60hz/simulation/functional/simulate_mti.do" type="ignore" timestamp="Tue Aug 09 21:40:18 GMT 2011" checksum="0x22B3C2B0"></File>
+ <File name="./clkgendcm_720p60hz/simulation/functional/simulate_ncsim.sh" type="ignore" timestamp="Tue Aug 09 21:40:18 GMT 2011" checksum="0x8FF291AA"></File>
+ <File name="./clkgendcm_720p60hz/simulation/functional/simulate_vcs.sh" type="ignore" timestamp="Tue Aug 09 21:40:19 GMT 2011" checksum="0x6CDC52B7"></File>
+ <File name="./clkgendcm_720p60hz/simulation/functional/ucli_commands.key" type="ignore" timestamp="Tue Aug 09 21:40:19 GMT 2011" checksum="0x15A5CE19"></File>
+ <File name="./clkgendcm_720p60hz/simulation/functional/vcs_session.tcl" type="ignore" timestamp="Tue Aug 09 21:40:19 GMT 2011" checksum="0x1A8D760C"></File>
+ <File name="./clkgendcm_720p60hz/simulation/functional/wave.do" type="ignore" timestamp="Tue Aug 09 21:40:18 GMT 2011" checksum="0xE0FCC1E4"></File>
+ <File name="./clkgendcm_720p60hz/simulation/functional/wave.sv" type="ignore" timestamp="Tue Aug 09 21:40:18 GMT 2011" checksum="0xF42F3C45"></File>
+ <File name="./clkgendcm_720p60hz.ejp" type="unknown" timestamp="Tue Aug 09 21:40:17 GMT 2011" checksum="0xDEF1B21C"></File>
+ <File name="./clkgendcm_720p60hz.v" type="verilog" timestamp="Tue Aug 09 21:40:17 GMT 2011" checksum="0xBB0CFF9A"></File>
+ <File name="./clkgendcm_720p60hz.veo" type="veo" timestamp="Tue Aug 09 21:40:17 GMT 2011" checksum="0x59A939F4"></File>
+ <File name="./clkgendcm_720p60hz_xmdf.tcl" type="tcl" timestamp="Tue Aug 09 21:40:18 GMT 2011" checksum="0x2BF520E1"></File>
+ </FileSet>
+ <FileSet generator="instantiation_template_generator">
+ <File name="./clkgendcm_720p60hz.veo" type="veo" timestamp="Tue Aug 09 21:40:20 GMT 2011" checksum="0x59A939F4"></File>
+ </FileSet>
+ <FileSet generator="asy_generator">
+ <File name="./clkgendcm_720p60hz.asy" type="asy" timestamp="Tue Aug 09 21:40:24 GMT 2011" checksum="0x4709598E"></File>
+ </FileSet>
+ <FileSet generator="xmdf_generator">
+ <File name="./xmdf_generator.xlog" type="ignore" timestamp="Tue Aug 09 21:40:26 GMT 2011" checksum="0xFFFFFFFF"></File>
+ </FileSet>
+ <FileSet generator="ise_generator">
+ <File name="./clkgendcm_720p60hz.gise" type="ignore" timestamp="Tue Aug 09 21:40:26 GMT 2011" checksum="0x62A4AF22"></File>
+ <File name="./clkgendcm_720p60hz.xise" type="ignore" timestamp="Tue Aug 09 21:40:26 GMT 2011" checksum="0x23EDC58D"></File>
+ </FileSet>
+ <FileSet generator="deliver_readme_generator">
+ <File name="./deliver_readme_generator.xlog" type="ignore" timestamp="Tue Aug 09 21:40:26 GMT 2011" checksum="0xFFFFFFFF"></File>
+ </FileSet>
+ <FileSet generator="flist_generator">
+ <File name="./clkgendcm_720p60hz_flist.txt" type="ignore" timestamp="Tue Aug 09 21:40:26 GMT 2011" checksum="0xC1C72AE1"></File>
+ </FileSet>
+ </FileSets>
+ </IPInstance>
+</BillOfMaterials>
diff --git a/ip/clk_wiz_v3_1_0/pa_cg_config_core_invoke.tcl b/ip/clk_wiz_v3_1_0/pa_cg_config_core_invoke.tcl new file mode 100755 index 0000000..d5918a7 --- /dev/null +++ b/ip/clk_wiz_v3_1_0/pa_cg_config_core_invoke.tcl @@ -0,0 +1,23 @@ +# Tcl script generated by PlanAhead
+
+set tclUtilsPath "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl"
+
+set cgProjectPath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/coregen.cgc"
+
+set ipName "clk_wiz_v3_1_0"
+
+set vlnv "xilinx.com:ip:clk_wiz:3.1"
+
+set cgPartSpec "6slx9-2tqg144"
+
+set bomFilePath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/pa_cg_bom.xml"
+
+set hdlType "Verilog"
+
+set chains "CUSTOMIZE_CHAIN INSTANTIATION_TEMPLATES_CHAIN"
+
+# configure the IP
+set result [source "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_config_core.tcl"]
+
+exit $result
+
diff --git a/ip/clk_wiz_v3_1_0/pa_cg_gen_core_invoke.tcl b/ip/clk_wiz_v3_1_0/pa_cg_gen_core_invoke.tcl new file mode 100755 index 0000000..f504ffb --- /dev/null +++ b/ip/clk_wiz_v3_1_0/pa_cg_gen_core_invoke.tcl @@ -0,0 +1,17 @@ +# Tcl script generated by PlanAhead
+
+set tclUtilsPath "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl"
+
+set cgProjectPath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/coregen.cgc"
+
+set ipName "clkgendcm_720p60hz"
+
+set chains "GENERATE_CHAIN"
+
+set bomFilePath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/pa_cg_bom.xml"
+
+# generate the IP
+set result [source "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_gen_core.tcl"]
+
+exit $result
+
diff --git a/ip/fifo_generator_v7_2_0/.lso b/ip/fifo_generator_v7_2_0/.lso new file mode 100755 index 0000000..05eddb4 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/.lso @@ -0,0 +1 @@ +fifo_generator_v7_2
diff --git a/ip/fifo_generator_v7_2_0/coregen.cgc b/ip/fifo_generator_v7_2_0/coregen.cgc new file mode 100755 index 0000000..b07d8e9 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/coregen.cgc @@ -0,0 +1,528 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" >
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>projects</spirit:library>
+ <spirit:name>coregen</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>fifo_2kx18</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="7.2" />
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">fifo_2kx18</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_HANDSHAKE_FLAG_OPTIONS_RDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WDCH">Empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DEPTH">2048</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WRCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WDCH">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DATA_WIDTH">18</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_AXIS">Full</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_HANDSHAKE_FLAG_OPTIONS_WRCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TKEEP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_BUSER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_READ_CHANNEL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WUSER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_AWUSER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_AXIS">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WACH">Full</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_AXIS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_AXIS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_AXIS">1024</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_RESET_VALUE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WACH">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXIS_TYPE">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WDCH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_FLAGS_RESET_VALUE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_WIDTH">64</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WACH">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH">2048</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_HANDSHAKE_FLAG_OPTIONS_WDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RACH">1022</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_OVERFLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RDCH">Full</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WACH_TYPE">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RDCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_UNDERFLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WRCH">Full</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_TYPE_AXI">Common_Clock</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDATA">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_ENABLE_TYPE">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RDCH">1024</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WRCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_SENSE">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TUSER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WRCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DATA_WIDTH">18</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WRCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RACH">Empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WRCH">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE">2045</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RACH">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADD_NGC_CONSTRAINT_AXI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS_AXI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_AXIS">1022</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RACH_TYPE">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PIN">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WACH">1022</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WDCH">Full</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TSTROBE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RACH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WDCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_AXIS">Empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WDCH">1024</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_AXIS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TLAST">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_AXIS">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_HANDSHAKE_FLAG_OPTIONS_RACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EXTRA_LOGIC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WACH">Empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RDCH">1022</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WRITE_CHANNEL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WDCH_TYPE">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WACH">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WRCH">1022</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_NEGATE_VALUE">2044</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_EMPTY_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_AXIS">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">Asynchronous_Reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRCH_TYPE">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DOUT_RESET">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WACH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RDCH">Empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_AXIS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_HANDSHAKE_FLAG_OPTIONS_AXIS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RDCH">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_FULL_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_SENSE">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WRCH">Empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RDCH_TYPE">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WRCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_NEGATE_VALUE">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WRCH">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_HANDSHAKE_FLAG_OPTIONS_WACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TREADY">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RACH">Full</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_ENABLE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WDCH">1022</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RUSER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EMBEDDED_REGISTERS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PERFORMANCE_OPTIONS">Standard_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_TYPE">AXI4_Stream</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ARUSER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDEST">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RACH">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RDCH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RESET_SYNCHRONIZATION">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ADDRESS_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RACH">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WRCH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">2kx18</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">18</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">2044</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">2048</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
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+ <xilinx:name>xmdf_generator</xilinx:name>
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+ <xilinx:name>./fifo_2kx18.gise</xilinx:name>
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+ <xilinx:subWorkingDirectory>./tmp/_cg</xilinx:subWorkingDirectory>
+ </xilinx:projectOptions>
+ <xilinx:part>
+ <xilinx:device>xc6slx9</xilinx:device>
+ <xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
+ <xilinx:package>tqg144</xilinx:package>
+ <xilinx:speedGrade>-2</xilinx:speedGrade>
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+ <xilinx:flowOptions>
+ <xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
+ <xilinx:designEntry>Verilog</xilinx:designEntry>
+ <xilinx:asySymbol>true</xilinx:asySymbol>
+ <xilinx:flowVendor>Foundation_ISE</xilinx:flowVendor>
+ <xilinx:addPads>false</xilinx:addPads>
+ <xilinx:removeRPMs>false</xilinx:removeRPMs>
+ <xilinx:createNDF>false</xilinx:createNDF>
+ <xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
+ <xilinx:formalVerification>false</xilinx:formalVerification>
+ </xilinx:flowOptions>
+ <xilinx:simulationOptions>
+ <xilinx:simulationModel>Behavioral</xilinx:simulationModel>
+ <xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
+ <xilinx:foundationSym>false</xilinx:foundationSym>
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+</spirit:design>
diff --git a/ip/fifo_generator_v7_2_0/coregen.cgp b/ip/fifo_generator_v7_2_0/coregen.cgp new file mode 100755 index 0000000..0725064 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/coregen.cgp @@ -0,0 +1,22 @@ +# Date: Tue Aug 09 21:31:41 2011 +
+SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +SET workingdirectory = ./tmp/ +
+# CRC: d3c0f20c
diff --git a/ip/fifo_generator_v7_2_0/coregen.log b/ip/fifo_generator_v7_2_0/coregen.log new file mode 100755 index 0000000..b090d84 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/coregen.log @@ -0,0 +1,44 @@ +CoreGen has not been configured with any user repositories. +CoreGen has been configured with the following Xilinx repositories: + - 'C:\Xilinx\13.1\ISE_DS\ISE\coregen\' [] +INFO:sim:927 - Generating component instance 'fifo_2kx18' of
+ 'xilinx.com:ip:fifo_generator:7.2' from
+ 'C:\Xilinx\13.1\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\fifo_gener
+ ator_v7_2\fifo_generator_v7_2.xcd'. +Resolving generic values... +Initializing IP model... +Finished initializing IP model. +Finished resolving generic values. +Generating IP... +WARNING:sim:975 - You are using Fifo Generator 7.2 which has been replaced with
+ a new version. This version of the core will be removed in a future release.
+ Cores in this state are not supported. +WARNING:sim:89 - A core named <fifo_2kx18> already exists in the output
+ directory. Output products for this core may be overwritten. +XST: HDL Parsing +XST: HDL Elaboration +XST: HDL Synthesis +XST: Advanced HDL Synthesis +XST: Low Level Synthesis +Generating Implementation files. +Picked up JAVA_TOOL_OPTIONS: -Xmx2048m +Generating NGC file. +Finished Generation. +Generating IP instantiation template... +Finished generating IP instantiation template. +Generating ASY schematic symbol... +Initializing IP model... +Finished initializing IP model. +Finished generating ASY schematic symbol. +Generating metadata file... +Finished generating metadata file. +Generating ISE project... +Finished generating ISE project.Generating README file... +Finished generating README file. +Generating FLIST file... +Finished FLIST file generation. +Preparing output directory... +Finished preparing output directory. +Moving files to output directory... +Finished moving files to output directory +Saved options for project 'coregen'. diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.asy b/ip/fifo_generator_v7_2_0/fifo_2kx18.asy new file mode 100755 index 0000000..b01eb08 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_2kx18 +RECTANGLE Normal 32 32 800 3712 +LINE Normal 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Wide 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName din[17:0] +PINATTR Polarity IN +LINE Normal 0 304 32 304 +PIN 0 304 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 496 32 496 +PIN 0 496 LEFT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Normal 832 240 800 240 +PIN 832 240 RIGHT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Wide 832 272 800 272 +PIN 832 272 RIGHT 36 +PINATTR PinName dout[17:0] +PINATTR Polarity OUT +LINE Normal 832 304 800 304 +PIN 832 304 RIGHT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 832 496 800 496 +PIN 832 496 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.gise b/ip/fifo_generator_v7_2_0/fifo_2kx18.gise new file mode 100755 index 0000000..4bcc080 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.gise @@ -0,0 +1,32 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_2kx18.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_2kx18.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_2kx18.veo" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.ngc b/ip/fifo_generator_v7_2_0/fifo_2kx18.ngc new file mode 100755 index 0000000..e1c560f --- /dev/null +++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.v b/ip/fifo_generator_v7_2_0/fifo_2kx18.v new file mode 100755 index 0000000..2583396 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.v @@ -0,0 +1,498 @@ +/*******************************************************************************
+* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
+* *
+* This file contains confidential and proprietary information *
+* of Xilinx, Inc. and is protected under U.S. and *
+* international copyright and other intellectual property *
+* laws. *
+* *
+* DISCLAIMER *
+* This disclaimer is not a license and does not grant any *
+* rights to the materials distributed herewith. Except as *
+* otherwise provided in a valid license issued to you by *
+* Xilinx, and to the maximum extent permitted by applicable *
+* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
+* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
+* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
+* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
+* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
+* (2) Xilinx shall not be liable (whether in contract or tort, *
+* including negligence, or under any other theory of *
+* liability) for any loss or damage of any kind or nature *
+* related to, arising under or in connection with these *
+* materials, including for any direct, or any indirect, *
+* special, incidental, or consequential loss or damage *
+* (including loss of data, profits, goodwill, or any type of *
+* loss or damage suffered as a result of any action brought *
+* by a third party) even if such damage or loss was *
+* reasonably foreseeable or Xilinx had been advised of the *
+* possibility of the same. *
+* *
+* CRITICAL APPLICATIONS *
+* Xilinx products are not designed or intended to be fail- *
+* safe, or for use in any application requiring fail-safe *
+* performance, such as life-support or safety devices or *
+* systems, Class III medical devices, nuclear facilities, *
+* applications related to the deployment of airbags, or any *
+* other applications that could lead to death, personal *
+* injury, or severe property or environmental damage *
+* (individually and collectively, "Critical *
+* Applications"). Customer assumes the sole risk and *
+* liability of any use of Xilinx products in Critical *
+* Applications, subject only to applicable laws and *
+* regulations governing limitations on product liability. *
+* *
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
+* PART OF THIS FILE AT ALL TIMES. *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_2kx18.v when simulating
+// the core, fifo_2kx18. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_2kx18(
+ rst,
+ wr_clk,
+ rd_clk,
+ din,
+ wr_en,
+ rd_en,
+ dout,
+ full,
+ empty);
+
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [17 : 0] din;
+input wr_en;
+input rd_en;
+output [17 : 0] dout;
+output full;
+output empty;
+
+// synthesis translate_off
+
+ FIFO_GENERATOR_V7_2 #(
+ .C_ADD_NGC_CONSTRAINT(0),
+ .C_APPLICATION_TYPE_AXIS(0),
+ .C_APPLICATION_TYPE_RACH(0),
+ .C_APPLICATION_TYPE_RDCH(0),
+ .C_APPLICATION_TYPE_WACH(0),
+ .C_APPLICATION_TYPE_WDCH(0),
+ .C_APPLICATION_TYPE_WRCH(0),
+ .C_AXIS_TDATA_WIDTH(64),
+ .C_AXIS_TDEST_WIDTH(4),
+ .C_AXIS_TID_WIDTH(8),
+ .C_AXIS_TKEEP_WIDTH(4),
+ .C_AXIS_TSTRB_WIDTH(4),
+ .C_AXIS_TUSER_WIDTH(4),
+ .C_AXIS_TYPE(0),
+ .C_AXI_ADDR_WIDTH(32),
+ .C_AXI_ARUSER_WIDTH(1),
+ .C_AXI_AWUSER_WIDTH(1),
+ .C_AXI_BUSER_WIDTH(1),
+ .C_AXI_DATA_WIDTH(64),
+ .C_AXI_ID_WIDTH(4),
+ .C_AXI_RUSER_WIDTH(1),
+ .C_AXI_TYPE(0),
+ .C_AXI_WUSER_WIDTH(1),
+ .C_COMMON_CLOCK(0),
+ .C_COUNT_TYPE(0),
+ .C_DATA_COUNT_WIDTH(11),
+ .C_DEFAULT_VALUE("BlankString"),
+ .C_DIN_WIDTH(18),
+ .C_DIN_WIDTH_AXIS(1),
+ .C_DIN_WIDTH_RACH(32),
+ .C_DIN_WIDTH_RDCH(64),
+ .C_DIN_WIDTH_WACH(32),
+ .C_DIN_WIDTH_WDCH(64),
+ .C_DIN_WIDTH_WRCH(2),
+ .C_DOUT_RST_VAL("0"),
+ .C_DOUT_WIDTH(18),
+ .C_ENABLE_RLOCS(0),
+ .C_ENABLE_RST_SYNC(1),
+ .C_ERROR_INJECTION_TYPE(0),
+ .C_ERROR_INJECTION_TYPE_AXIS(0),
+ .C_ERROR_INJECTION_TYPE_RACH(0),
+ .C_ERROR_INJECTION_TYPE_RDCH(0),
+ .C_ERROR_INJECTION_TYPE_WACH(0),
+ .C_ERROR_INJECTION_TYPE_WDCH(0),
+ .C_ERROR_INJECTION_TYPE_WRCH(0),
+ .C_FAMILY("spartan6"),
+ .C_FULL_FLAGS_RST_VAL(1),
+ .C_HAS_ALMOST_EMPTY(0),
+ .C_HAS_ALMOST_FULL(0),
+ .C_HAS_AXIS_TDATA(0),
+ .C_HAS_AXIS_TDEST(0),
+ .C_HAS_AXIS_TID(0),
+ .C_HAS_AXIS_TKEEP(0),
+ .C_HAS_AXIS_TLAST(0),
+ .C_HAS_AXIS_TREADY(1),
+ .C_HAS_AXIS_TSTRB(0),
+ .C_HAS_AXIS_TUSER(0),
+ .C_HAS_AXI_ARUSER(0),
+ .C_HAS_AXI_AWUSER(0),
+ .C_HAS_AXI_BUSER(0),
+ .C_HAS_AXI_RD_CHANNEL(0),
+ .C_HAS_AXI_RUSER(0),
+ .C_HAS_AXI_WR_CHANNEL(0),
+ .C_HAS_AXI_WUSER(0),
+ .C_HAS_BACKUP(0),
+ .C_HAS_DATA_COUNT(0),
+ .C_HAS_DATA_COUNTS_AXIS(0),
+ .C_HAS_DATA_COUNTS_RACH(0),
+ .C_HAS_DATA_COUNTS_RDCH(0),
+ .C_HAS_DATA_COUNTS_WACH(0),
+ .C_HAS_DATA_COUNTS_WDCH(0),
+ .C_HAS_DATA_COUNTS_WRCH(0),
+ .C_HAS_INT_CLK(0),
+ .C_HAS_MASTER_CE(0),
+ .C_HAS_MEMINIT_FILE(0),
+ .C_HAS_OVERFLOW(0),
+ .C_HAS_PROG_FLAGS_AXIS(0),
+ .C_HAS_PROG_FLAGS_RACH(0),
+ .C_HAS_PROG_FLAGS_RDCH(0),
+ .C_HAS_PROG_FLAGS_WACH(0),
+ .C_HAS_PROG_FLAGS_WDCH(0),
+ .C_HAS_PROG_FLAGS_WRCH(0),
+ .C_HAS_RD_DATA_COUNT(0),
+ .C_HAS_RD_RST(0),
+ .C_HAS_RST(1),
+ .C_HAS_SLAVE_CE(0),
+ .C_HAS_SRST(0),
+ .C_HAS_UNDERFLOW(0),
+ .C_HAS_VALID(0),
+ .C_HAS_WR_ACK(0),
+ .C_HAS_WR_DATA_COUNT(0),
+ .C_HAS_WR_RST(0),
+ .C_IMPLEMENTATION_TYPE(2),
+ .C_IMPLEMENTATION_TYPE_AXIS(1),
+ .C_IMPLEMENTATION_TYPE_RACH(1),
+ .C_IMPLEMENTATION_TYPE_RDCH(1),
+ .C_IMPLEMENTATION_TYPE_WACH(1),
+ .C_IMPLEMENTATION_TYPE_WDCH(1),
+ .C_IMPLEMENTATION_TYPE_WRCH(1),
+ .C_INIT_WR_PNTR_VAL(0),
+ .C_INTERFACE_TYPE(0),
+ .C_MEMORY_TYPE(1),
+ .C_MIF_FILE_NAME("BlankString"),
+ .C_MSGON_VAL(1),
+ .C_OPTIMIZATION_MODE(0),
+ .C_OVERFLOW_LOW(0),
+ .C_PRELOAD_LATENCY(1),
+ .C_PRELOAD_REGS(0),
+ .C_PRIM_FIFO_TYPE("2kx18"),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
+ .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
+ .C_PROG_EMPTY_TYPE(0),
+ .C_PROG_EMPTY_TYPE_AXIS(5),
+ .C_PROG_EMPTY_TYPE_RACH(5),
+ .C_PROG_EMPTY_TYPE_RDCH(5),
+ .C_PROG_EMPTY_TYPE_WACH(5),
+ .C_PROG_EMPTY_TYPE_WDCH(5),
+ .C_PROG_EMPTY_TYPE_WRCH(5),
+ .C_PROG_FULL_THRESH_ASSERT_VAL(2045),
+ .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
+ .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
+ .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
+ .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
+ .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
+ .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
+ .C_PROG_FULL_THRESH_NEGATE_VAL(2044),
+ .C_PROG_FULL_TYPE(0),
+ .C_PROG_FULL_TYPE_AXIS(5),
+ .C_PROG_FULL_TYPE_RACH(5),
+ .C_PROG_FULL_TYPE_RDCH(5),
+ .C_PROG_FULL_TYPE_WACH(5),
+ .C_PROG_FULL_TYPE_WDCH(5),
+ .C_PROG_FULL_TYPE_WRCH(5),
+ .C_RACH_TYPE(0),
+ .C_RDCH_TYPE(0),
+ .C_RD_DATA_COUNT_WIDTH(11),
+ .C_RD_DEPTH(2048),
+ .C_RD_FREQ(1),
+ .C_RD_PNTR_WIDTH(11),
+ .C_REG_SLICE_MODE_AXIS(0),
+ .C_REG_SLICE_MODE_RACH(0),
+ .C_REG_SLICE_MODE_RDCH(0),
+ .C_REG_SLICE_MODE_WACH(0),
+ .C_REG_SLICE_MODE_WDCH(0),
+ .C_REG_SLICE_MODE_WRCH(0),
+ .C_UNDERFLOW_LOW(0),
+ .C_USE_COMMON_OVERFLOW(0),
+ .C_USE_COMMON_UNDERFLOW(0),
+ .C_USE_DEFAULT_SETTINGS(0),
+ .C_USE_DOUT_RST(0),
+ .C_USE_ECC(0),
+ .C_USE_ECC_AXIS(0),
+ .C_USE_ECC_RACH(0),
+ .C_USE_ECC_RDCH(0),
+ .C_USE_ECC_WACH(0),
+ .C_USE_ECC_WDCH(0),
+ .C_USE_ECC_WRCH(0),
+ .C_USE_EMBEDDED_REG(0),
+ .C_USE_FIFO16_FLAGS(0),
+ .C_USE_FWFT_DATA_COUNT(0),
+ .C_VALID_LOW(0),
+ .C_WACH_TYPE(0),
+ .C_WDCH_TYPE(0),
+ .C_WRCH_TYPE(0),
+ .C_WR_ACK_LOW(0),
+ .C_WR_DATA_COUNT_WIDTH(11),
+ .C_WR_DEPTH(2048),
+ .C_WR_DEPTH_AXIS(1024),
+ .C_WR_DEPTH_RACH(16),
+ .C_WR_DEPTH_RDCH(1024),
+ .C_WR_DEPTH_WACH(16),
+ .C_WR_DEPTH_WDCH(1024),
+ .C_WR_DEPTH_WRCH(16),
+ .C_WR_FREQ(1),
+ .C_WR_PNTR_WIDTH(11),
+ .C_WR_PNTR_WIDTH_AXIS(10),
+ .C_WR_PNTR_WIDTH_RACH(4),
+ .C_WR_PNTR_WIDTH_RDCH(10),
+ .C_WR_PNTR_WIDTH_WACH(4),
+ .C_WR_PNTR_WIDTH_WDCH(10),
+ .C_WR_PNTR_WIDTH_WRCH(4),
+ .C_WR_RESPONSE_LATENCY(1))
+ inst (
+ .RST(rst),
+ .WR_CLK(wr_clk),
+ .RD_CLK(rd_clk),
+ .DIN(din),
+ .WR_EN(wr_en),
+ .RD_EN(rd_en),
+ .DOUT(dout),
+ .FULL(full),
+ .EMPTY(empty),
+ .BACKUP(),
+ .BACKUP_MARKER(),
+ .CLK(),
+ .SRST(),
+ .WR_RST(),
+ .RD_RST(),
+ .PROG_EMPTY_THRESH(),
+ .PROG_EMPTY_THRESH_ASSERT(),
+ .PROG_EMPTY_THRESH_NEGATE(),
+ .PROG_FULL_THRESH(),
+ .PROG_FULL_THRESH_ASSERT(),
+ .PROG_FULL_THRESH_NEGATE(),
+ .INT_CLK(),
+ .INJECTDBITERR(),
+ .INJECTSBITERR(),
+ .ALMOST_FULL(),
+ .WR_ACK(),
+ .OVERFLOW(),
+ .ALMOST_EMPTY(),
+ .VALID(),
+ .UNDERFLOW(),
+ .DATA_COUNT(),
+ .RD_DATA_COUNT(),
+ .WR_DATA_COUNT(),
+ .PROG_FULL(),
+ .PROG_EMPTY(),
+ .SBITERR(),
+ .DBITERR(),
+ .M_ACLK(),
+ .S_ACLK(),
+ .S_ARESETN(),
+ .M_ACLK_EN(),
+ .S_ACLK_EN(),
+ .S_AXI_AWID(),
+ .S_AXI_AWADDR(),
+ .S_AXI_AWLEN(),
+ .S_AXI_AWSIZE(),
+ .S_AXI_AWBURST(),
+ .S_AXI_AWLOCK(),
+ .S_AXI_AWCACHE(),
+ .S_AXI_AWPROT(),
+ .S_AXI_AWQOS(),
+ .S_AXI_AWREGION(),
+ .S_AXI_AWUSER(),
+ .S_AXI_AWVALID(),
+ .S_AXI_AWREADY(),
+ .S_AXI_WID(),
+ .S_AXI_WDATA(),
+ .S_AXI_WSTRB(),
+ .S_AXI_WLAST(),
+ .S_AXI_WUSER(),
+ .S_AXI_WVALID(),
+ .S_AXI_WREADY(),
+ .S_AXI_BID(),
+ .S_AXI_BRESP(),
+ .S_AXI_BUSER(),
+ .S_AXI_BVALID(),
+ .S_AXI_BREADY(),
+ .M_AXI_AWID(),
+ .M_AXI_AWADDR(),
+ .M_AXI_AWLEN(),
+ .M_AXI_AWSIZE(),
+ .M_AXI_AWBURST(),
+ .M_AXI_AWLOCK(),
+ .M_AXI_AWCACHE(),
+ .M_AXI_AWPROT(),
+ .M_AXI_AWQOS(),
+ .M_AXI_AWREGION(),
+ .M_AXI_AWUSER(),
+ .M_AXI_AWVALID(),
+ .M_AXI_AWREADY(),
+ .M_AXI_WID(),
+ .M_AXI_WDATA(),
+ .M_AXI_WSTRB(),
+ .M_AXI_WLAST(),
+ .M_AXI_WUSER(),
+ .M_AXI_WVALID(),
+ .M_AXI_WREADY(),
+ .M_AXI_BID(),
+ .M_AXI_BRESP(),
+ .M_AXI_BUSER(),
+ .M_AXI_BVALID(),
+ .M_AXI_BREADY(),
+ .S_AXI_ARID(),
+ .S_AXI_ARADDR(),
+ .S_AXI_ARLEN(),
+ .S_AXI_ARSIZE(),
+ .S_AXI_ARBURST(),
+ .S_AXI_ARLOCK(),
+ .S_AXI_ARCACHE(),
+ .S_AXI_ARPROT(),
+ .S_AXI_ARQOS(),
+ .S_AXI_ARREGION(),
+ .S_AXI_ARUSER(),
+ .S_AXI_ARVALID(),
+ .S_AXI_ARREADY(),
+ .S_AXI_RID(),
+ .S_AXI_RDATA(),
+ .S_AXI_RRESP(),
+ .S_AXI_RLAST(),
+ .S_AXI_RUSER(),
+ .S_AXI_RVALID(),
+ .S_AXI_RREADY(),
+ .M_AXI_ARID(),
+ .M_AXI_ARADDR(),
+ .M_AXI_ARLEN(),
+ .M_AXI_ARSIZE(),
+ .M_AXI_ARBURST(),
+ .M_AXI_ARLOCK(),
+ .M_AXI_ARCACHE(),
+ .M_AXI_ARPROT(),
+ .M_AXI_ARQOS(),
+ .M_AXI_ARREGION(),
+ .M_AXI_ARUSER(),
+ .M_AXI_ARVALID(),
+ .M_AXI_ARREADY(),
+ .M_AXI_RID(),
+ .M_AXI_RDATA(),
+ .M_AXI_RRESP(),
+ .M_AXI_RLAST(),
+ .M_AXI_RUSER(),
+ .M_AXI_RVALID(),
+ .M_AXI_RREADY(),
+ .S_AXIS_TVALID(),
+ .S_AXIS_TREADY(),
+ .S_AXIS_TDATA(),
+ .S_AXIS_TSTRB(),
+ .S_AXIS_TKEEP(),
+ .S_AXIS_TLAST(),
+ .S_AXIS_TID(),
+ .S_AXIS_TDEST(),
+ .S_AXIS_TUSER(),
+ .M_AXIS_TVALID(),
+ .M_AXIS_TREADY(),
+ .M_AXIS_TDATA(),
+ .M_AXIS_TSTRB(),
+ .M_AXIS_TKEEP(),
+ .M_AXIS_TLAST(),
+ .M_AXIS_TID(),
+ .M_AXIS_TDEST(),
+ .M_AXIS_TUSER(),
+ .AXI_AW_INJECTSBITERR(),
+ .AXI_AW_INJECTDBITERR(),
+ .AXI_AW_PROG_FULL_THRESH(),
+ .AXI_AW_PROG_EMPTY_THRESH(),
+ .AXI_AW_DATA_COUNT(),
+ .AXI_AW_WR_DATA_COUNT(),
+ .AXI_AW_RD_DATA_COUNT(),
+ .AXI_AW_SBITERR(),
+ .AXI_AW_DBITERR(),
+ .AXI_AW_OVERFLOW(),
+ .AXI_AW_UNDERFLOW(),
+ .AXI_W_INJECTSBITERR(),
+ .AXI_W_INJECTDBITERR(),
+ .AXI_W_PROG_FULL_THRESH(),
+ .AXI_W_PROG_EMPTY_THRESH(),
+ .AXI_W_DATA_COUNT(),
+ .AXI_W_WR_DATA_COUNT(),
+ .AXI_W_RD_DATA_COUNT(),
+ .AXI_W_SBITERR(),
+ .AXI_W_DBITERR(),
+ .AXI_W_OVERFLOW(),
+ .AXI_W_UNDERFLOW(),
+ .AXI_B_INJECTSBITERR(),
+ .AXI_B_INJECTDBITERR(),
+ .AXI_B_PROG_FULL_THRESH(),
+ .AXI_B_PROG_EMPTY_THRESH(),
+ .AXI_B_DATA_COUNT(),
+ .AXI_B_WR_DATA_COUNT(),
+ .AXI_B_RD_DATA_COUNT(),
+ .AXI_B_SBITERR(),
+ .AXI_B_DBITERR(),
+ .AXI_B_OVERFLOW(),
+ .AXI_B_UNDERFLOW(),
+ .AXI_AR_INJECTSBITERR(),
+ .AXI_AR_INJECTDBITERR(),
+ .AXI_AR_PROG_FULL_THRESH(),
+ .AXI_AR_PROG_EMPTY_THRESH(),
+ .AXI_AR_DATA_COUNT(),
+ .AXI_AR_WR_DATA_COUNT(),
+ .AXI_AR_RD_DATA_COUNT(),
+ .AXI_AR_SBITERR(),
+ .AXI_AR_DBITERR(),
+ .AXI_AR_OVERFLOW(),
+ .AXI_AR_UNDERFLOW(),
+ .AXI_R_INJECTSBITERR(),
+ .AXI_R_INJECTDBITERR(),
+ .AXI_R_PROG_FULL_THRESH(),
+ .AXI_R_PROG_EMPTY_THRESH(),
+ .AXI_R_DATA_COUNT(),
+ .AXI_R_WR_DATA_COUNT(),
+ .AXI_R_RD_DATA_COUNT(),
+ .AXI_R_SBITERR(),
+ .AXI_R_DBITERR(),
+ .AXI_R_OVERFLOW(),
+ .AXI_R_UNDERFLOW(),
+ .AXIS_INJECTSBITERR(),
+ .AXIS_INJECTDBITERR(),
+ .AXIS_PROG_FULL_THRESH(),
+ .AXIS_PROG_EMPTY_THRESH(),
+ .AXIS_DATA_COUNT(),
+ .AXIS_WR_DATA_COUNT(),
+ .AXIS_RD_DATA_COUNT(),
+ .AXIS_SBITERR(),
+ .AXIS_DBITERR(),
+ .AXIS_OVERFLOW(),
+ .AXIS_UNDERFLOW());
+
+
+// synthesis translate_on
+
+// XST black box declaration
+// box_type "black_box"
+// synthesis attribute box_type of fifo_2kx18 is "black_box"
+
+endmodule
+
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.veo b/ip/fifo_generator_v7_2_0/fifo_2kx18.veo new file mode 100755 index 0000000..be52216 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.veo @@ -0,0 +1,70 @@ +/*******************************************************************************
+* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
+* *
+* This file contains confidential and proprietary information *
+* of Xilinx, Inc. and is protected under U.S. and *
+* international copyright and other intellectual property *
+* laws. *
+* *
+* DISCLAIMER *
+* This disclaimer is not a license and does not grant any *
+* rights to the materials distributed herewith. Except as *
+* otherwise provided in a valid license issued to you by *
+* Xilinx, and to the maximum extent permitted by applicable *
+* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
+* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
+* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
+* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
+* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
+* (2) Xilinx shall not be liable (whether in contract or tort, *
+* including negligence, or under any other theory of *
+* liability) for any loss or damage of any kind or nature *
+* related to, arising under or in connection with these *
+* materials, including for any direct, or any indirect, *
+* special, incidental, or consequential loss or damage *
+* (including loss of data, profits, goodwill, or any type of *
+* loss or damage suffered as a result of any action brought *
+* by a third party) even if such damage or loss was *
+* reasonably foreseeable or Xilinx had been advised of the *
+* possibility of the same. *
+* *
+* CRITICAL APPLICATIONS *
+* Xilinx products are not designed or intended to be fail- *
+* safe, or for use in any application requiring fail-safe *
+* performance, such as life-support or safety devices or *
+* systems, Class III medical devices, nuclear facilities, *
+* applications related to the deployment of airbags, or any *
+* other applications that could lead to death, personal *
+* injury, or severe property or environmental damage *
+* (individually and collectively, "Critical *
+* Applications"). Customer assumes the sole risk and *
+* liability of any use of Xilinx products in Critical *
+* Applications, subject only to applicable laws and *
+* regulations governing limitations on product liability. *
+* *
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
+* PART OF THIS FILE AT ALL TIMES. *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_2kx18 YourInstanceName (
+ .rst(rst), // input rst
+ .wr_clk(wr_clk), // input wr_clk
+ .rd_clk(rd_clk), // input rd_clk
+ .din(din), // input [17 : 0] din
+ .wr_en(wr_en), // input wr_en
+ .rd_en(rd_en), // input rd_en
+ .dout(dout), // ouput [17 : 0] dout
+ .full(full), // ouput full
+ .empty(empty)); // ouput empty
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_2kx18.v when simulating
+// the core, fifo_2kx18. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.xco b/ip/fifo_generator_v7_2_0/fifo_2kx18.xco new file mode 100755 index 0000000..f892af2 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.xco @@ -0,0 +1,203 @@ +##############################################################
+#
+# Xilinx Core Generator version 13.1
+# Date: Tue Aug 09 21:46:42 2011
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 7.2
+# END Select
+# BEGIN Parameters
+CSET add_ngc_constraint_axi=false
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET aruser_width=1
+CSET awuser_width=1
+CSET axi_address_width=32
+CSET axi_data_width=64
+CSET axi_type=AXI4_Stream
+CSET axis_type=FIFO
+CSET buser_width=1
+CSET clock_enable_type=Slave_Interface_Clock_Enable
+CSET clock_type_axi=Common_Clock
+CSET component_name=fifo_2kx18
+CSET data_count=false
+CSET data_count_width=11
+CSET disable_timing_violations=false
+CSET disable_timing_violations_axi=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_assert_value_axis=1022
+CSET empty_threshold_assert_value_rach=1022
+CSET empty_threshold_assert_value_rdch=1022
+CSET empty_threshold_assert_value_wach=1022
+CSET empty_threshold_assert_value_wdch=1022
+CSET empty_threshold_assert_value_wrch=1022
+CSET empty_threshold_negate_value=3
+CSET enable_aruser=false
+CSET enable_awuser=false
+CSET enable_buser=false
+CSET enable_common_overflow=false
+CSET enable_common_underflow=false
+CSET enable_data_counts_axis=false
+CSET enable_data_counts_rach=false
+CSET enable_data_counts_rdch=false
+CSET enable_data_counts_wach=false
+CSET enable_data_counts_wdch=false
+CSET enable_data_counts_wrch=false
+CSET enable_ecc=false
+CSET enable_ecc_axis=false
+CSET enable_ecc_rach=false
+CSET enable_ecc_rdch=false
+CSET enable_ecc_wach=false
+CSET enable_ecc_wdch=false
+CSET enable_ecc_wrch=false
+CSET enable_handshake_flag_options_axis=false
+CSET enable_handshake_flag_options_rach=false
+CSET enable_handshake_flag_options_rdch=false
+CSET enable_handshake_flag_options_wach=false
+CSET enable_handshake_flag_options_wdch=false
+CSET enable_handshake_flag_options_wrch=false
+CSET enable_read_channel=false
+CSET enable_reset_synchronization=true
+CSET enable_ruser=false
+CSET enable_tdata=false
+CSET enable_tdest=false
+CSET enable_tid=false
+CSET enable_tkeep=false
+CSET enable_tlast=false
+CSET enable_tready=true
+CSET enable_tstrobe=false
+CSET enable_tuser=false
+CSET enable_write_channel=false
+CSET enable_wuser=false
+CSET fifo_application_type_axis=Data_FIFO
+CSET fifo_application_type_rach=Data_FIFO
+CSET fifo_application_type_rdch=Data_FIFO
+CSET fifo_application_type_wach=Data_FIFO
+CSET fifo_application_type_wdch=Data_FIFO
+CSET fifo_application_type_wrch=Data_FIFO
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET fifo_implementation_axis=Common_Clock_Block_RAM
+CSET fifo_implementation_rach=Common_Clock_Block_RAM
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wach=Common_Clock_Block_RAM
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=2045
+CSET full_threshold_assert_value_axis=1023
+CSET full_threshold_assert_value_rach=1023
+CSET full_threshold_assert_value_rdch=1023
+CSET full_threshold_assert_value_wach=1023
+CSET full_threshold_assert_value_wdch=1023
+CSET full_threshold_assert_value_wrch=1023
+CSET full_threshold_negate_value=2044
+CSET id_width=4
+CSET inject_dbit_error=false
+CSET inject_dbit_error_axis=false
+CSET inject_dbit_error_rach=false
+CSET inject_dbit_error_rdch=false
+CSET inject_dbit_error_wach=false
+CSET inject_dbit_error_wdch=false
+CSET inject_dbit_error_wrch=false
+CSET inject_sbit_error=false
+CSET inject_sbit_error_axis=false
+CSET inject_sbit_error_rach=false
+CSET inject_sbit_error_rdch=false
+CSET inject_sbit_error_wach=false
+CSET inject_sbit_error_wdch=false
+CSET inject_sbit_error_wrch=false
+CSET input_data_width=18
+CSET input_depth=2048
+CSET input_depth_axis=1024
+CSET input_depth_rach=16
+CSET input_depth_rdch=1024
+CSET input_depth_wach=16
+CSET input_depth_wdch=1024
+CSET input_depth_wrch=16
+CSET interface_type=Native
+CSET output_data_width=18
+CSET output_depth=2048
+CSET overflow_flag=false
+CSET overflow_flag_axi=false
+CSET overflow_sense=Active_High
+CSET overflow_sense_axi=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_axis=Empty
+CSET programmable_empty_type_rach=Empty
+CSET programmable_empty_type_rdch=Empty
+CSET programmable_empty_type_wach=Empty
+CSET programmable_empty_type_wdch=Empty
+CSET programmable_empty_type_wrch=Empty
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET programmable_full_type_axis=Full
+CSET programmable_full_type_rach=Full
+CSET programmable_full_type_rdch=Full
+CSET programmable_full_type_wach=Full
+CSET programmable_full_type_wdch=Full
+CSET programmable_full_type_wrch=Full
+CSET rach_type=FIFO
+CSET rdch_type=FIFO
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=11
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET ruser_width=1
+CSET tdata_width=64
+CSET tdest_width=4
+CSET tid_width=8
+CSET tkeep_width=4
+CSET tstrb_width=4
+CSET tuser_width=4
+CSET underflow_flag=false
+CSET underflow_flag_axi=false
+CSET underflow_sense=Active_High
+CSET underflow_sense_axi=Active_High
+CSET use_clock_enable=false
+CSET use_dout_reset=false
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET wach_type=FIFO
+CSET wdch_type=FIFO
+CSET wrch_type=FIFO
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=11
+CSET wuser_width=1
+# END Parameters
+GENERATE
+# CRC: 5a428ec2
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.xise b/ip/fifo_generator_v7_2_0/fifo_2kx18.xise new file mode 100755 index 0000000..284f7d3 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.xise @@ -0,0 +1,399 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="fifo_2kx18.ngc" xil_pn:type="FILE_NGC"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> + </file> + <file xil_pn:name="fifo_2kx18.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="3"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/> + </file> + </files> + + <properties> + <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Add I/O 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xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> + <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/> + <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/> + <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/> + <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> + <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> + <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/> + <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> + <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> + <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/> + <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> + <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> + <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/> + <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/> + <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/> + <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/> + <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> + <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Output File Name" xil_pn:value="fifo_2kx18" xil_pn:valueState="default"/> + <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/> + <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/> + <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> + <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> + <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> + <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> + <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="fifo_2kx18_map.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="fifo_2kx18_timesim.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="fifo_2kx18_synthesis.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="fifo_2kx18_translate.v" xil_pn:valueState="default"/> + <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> + <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/> + <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> + <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> + <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> + <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/> + <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> + <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> + <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> + <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> + <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/> + <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> + <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/> + <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> + <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> + <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> + <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> + <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/> + <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_2kx18" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-08-10T05:47:09" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C3C07357CF834C1EB043358346420692" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18_flist.txt b/ip/fifo_generator_v7_2_0/fifo_2kx18_flist.txt new file mode 100755 index 0000000..fb00e08 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/fifo_2kx18_flist.txt @@ -0,0 +1,12 @@ +# Output products list for <fifo_2kx18>
+fifo_2kx18.asy
+fifo_2kx18.gise
+fifo_2kx18.ngc
+fifo_2kx18.v
+fifo_2kx18.veo
+fifo_2kx18.xco
+fifo_2kx18.xise
+fifo_2kx18_flist.txt
+fifo_2kx18_xmdf.tcl
+fifo_generator_readme.txt
+fifo_generator_ug175.pdf
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18_xmdf.tcl b/ip/fifo_generator_v7_2_0/fifo_2kx18_xmdf.tcl new file mode 100755 index 0000000..629d396 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/fifo_2kx18_xmdf.tcl @@ -0,0 +1,76 @@ +# The package naming convention is <core_name>_xmdf
+package provide fifo_2kx18_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_2kx18_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_2kx18_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_2kx18
+}
+# ::fifo_2kx18_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_2kx18_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_2kx18.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_2kx18.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_2kx18.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_2kx18.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_2kx18.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_2kx18_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_2kx18
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/ip/fifo_generator_v7_2_0/fifo_generator_readme.txt b/ip/fifo_generator_v7_2_0/fifo_generator_readme.txt new file mode 100755 index 0000000..3cc2fc3 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/fifo_generator_readme.txt @@ -0,0 +1,185 @@ + Core Name: Xilinx LogiCORE FIFO Generator + Version: 7.2 + Release Date: September 21, 2010 + + +================================================================================ + +This document contains the following sections: + +1. Introduction +2. New Features +3. Supported Devices +4. Resolved Issues +5. Known Issues +6. Technical Support +7. Core Release History +8. Legal Disclaimer + +================================================================================ + +1. INTRODUCTION + +For the most recent updates to the IP installation instructions for this core, +please go to: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + + +For software requirements, please go to the "Software Requirements" link on that page. + + +This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v7.2 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm + + +2. NEW FEATURES + + - AXI4 (AXI4-Stream, AXI4 and AXI4-Lite) Support (Spartan-6 and Virtex-6 devices only) + - ISE 12.3 software support + +3. SUPPORTED DEVICES + + The following device families are supported by the core for this release. + + - Virtex-6 XC CXT/LXT/SXT/HXT + - Virtex-6 XQ LXT/SXT + - Virtex-6 -1L XC LXT/SXT + + - Spartan-6 XC LX/LXT + - Spartan-6 XA + - Spartan-6 XQ LX/LXT + - Spartan-6 -1L XC LX + + - Virtex-5 XC LX/LXT/SXT/TXT/FXT + - Virtex-5 XQ LX/ LXT/SXT/FXT + + - Virtex-4 XC LX/SX/FX + - Virtex-4 XQ LX/SX/FX + - Virtex-4 XQR LX/SX/FX + + - Spartan-3 XC + - Spartan-3 XA + - Spartan-3A XC 3A / 3A DSP / 3AN DSP + - Spartan-3A XA 3A / 3A DSP + - Spartan-3E XC + - Spartan-3E XA + +4. RESOLVED ISSUES + + - In the FIFO Generator GUI, navigation buttons at the bottom are not accessible unless the screen resolution + is set to 1600x1200 or 1900x1200. + - CR 568630 + + - The FIFO Generator GUI does not generate the core if the depth is reduced after the data count option is selected. + - CR 570314 + +5. KNOWN ISSUES + + The following are known issues for v7.2 of this core at time of release: + + - In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) + into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, + page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should. + - CR 467240 + - AR 31379 + + - The FIFO Generator GUI does not generate the core if the Family is Spartan-6, and FIFO Implementation Type is + either Common or Independent Clock Block RAM, and the depth is 64K and the width is 36. + - CR 570041 + - AR 37201 + + The most recent information, including known issues, workarounds, and + resolutions for this version is provided in the IP Release Notes User Guide + located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + + +6. TECHNICAL SUPPORT + + To obtain technical support, create a WebCase at www.xilinx.com/support. + Questions are routed to a team with expertise using this product. + + Xilinx provides technical support for use of this product when used + according to the guidelines described in the core documentation, and + cannot guarantee timing, functionality, or support of this product for + designs that do not follow specified guidelines. + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support +07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support +06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support +09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support +06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support +09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes +03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes +10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs +08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO +04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support +09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support +07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support +01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3 +08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2 +04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1 +11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0 +05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support +04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release +================================================================================ + +8. Legal Disclaimer + + (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/ip/fifo_generator_v7_2_0/pa_cg_bom.xml b/ip/fifo_generator_v7_2_0/pa_cg_bom.xml new file mode 100755 index 0000000..ec972e8 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/pa_cg_bom.xml @@ -0,0 +1,39 @@ +<?xml version="1.0"?>
+<BillOfMaterials Version="1" Minor="2">
+ <IPInstance name="fifo_2kx18">
+ <FileSets>
+ <FileSet generator="model_parameter_resolution_generator">
+ <File name="./model_parameter_resolution_generator.xlog" type="ignore" timestamp="Tue Aug 09 21:47:10 GMT 2011" checksum="0xFFFFFFFF"></File>
+ </FileSet>
+ <FileSet generator="ip_xco_generator">
+ <File name="./fifo_2kx18.xco" type="xco" timestamp="Tue Aug 09 21:46:42 GMT 2011" checksum="0x200AB8B2"></File>
+ </FileSet>
+ <FileSet generator="ngc_netlist_generator">
+ <File name="./fifo_2kx18.ngc" type="ngc" timestamp="Tue Aug 09 21:47:05 GMT 2011" checksum="0x80830D9F"></File>
+ <File name="./fifo_2kx18.v" type="verilog" timestamp="Tue Aug 09 21:46:58 GMT 2011" checksum="0x6726F87E"></File>
+ <File name="./fifo_2kx18.veo" type="veo" timestamp="Tue Aug 09 21:46:58 GMT 2011" checksum="0x368CEE5B"></File>
+ <File name="./fifo_generator_readme.txt" type="txt" timestamp="Tue Aug 09 21:46:58 GMT 2011" checksum="0x8C1691E3"></File>
+ <File name="./fifo_generator_ug175.pdf" type="pdf" timestamp="Tue Aug 09 21:46:58 GMT 2011" checksum="0x7B853EF8"></File>
+ </FileSet>
+ <FileSet generator="instantiation_template_generator">
+ <File name="./fifo_2kx18.veo" type="veo" timestamp="Tue Aug 09 21:47:05 GMT 2011" checksum="0x368CEE5B"></File>
+ </FileSet>
+ <FileSet generator="asy_generator">
+ <File name="./fifo_2kx18.asy" type="asy" timestamp="Tue Aug 09 21:47:08 GMT 2011" checksum="0x903A7B6F"></File>
+ </FileSet>
+ <FileSet generator="xmdf_generator">
+ <File name="./fifo_2kx18_xmdf.tcl" type="tclXmdf" timestamp="Tue Aug 09 21:47:08 GMT 2011" checksum="0xBF5DD5B7"></File>
+ </FileSet>
+ <FileSet generator="ise_generator">
+ <File name="./fifo_2kx18.gise" type="ignore" timestamp="Tue Aug 09 21:47:10 GMT 2011" checksum="0xAC308EE9"></File>
+ <File name="./fifo_2kx18.xise" type="ignore" timestamp="Tue Aug 09 21:47:10 GMT 2011" checksum="0xC62EA0FE"></File>
+ </FileSet>
+ <FileSet generator="deliver_readme_generator">
+ <File name="./deliver_readme_generator.xlog" type="ignore" timestamp="Tue Aug 09 21:47:10 GMT 2011" checksum="0xFFFFFFFF"></File>
+ </FileSet>
+ <FileSet generator="flist_generator">
+ <File name="./fifo_2kx18_flist.txt" type="ignore" timestamp="Tue Aug 09 21:47:10 GMT 2011" checksum="0x64B4445D"></File>
+ </FileSet>
+ </FileSets>
+ </IPInstance>
+</BillOfMaterials>
diff --git a/ip/fifo_generator_v7_2_0/pa_cg_gen_core_invoke.tcl b/ip/fifo_generator_v7_2_0/pa_cg_gen_core_invoke.tcl new file mode 100755 index 0000000..1863d00 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/pa_cg_gen_core_invoke.tcl @@ -0,0 +1,17 @@ +# Tcl script generated by PlanAhead
+
+set tclUtilsPath "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl"
+
+set cgProjectPath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/coregen.cgc"
+
+set ipName "fifo_2kx18"
+
+set chains "GENERATE_CHAIN"
+
+set bomFilePath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/pa_cg_bom.xml"
+
+# generate the IP
+set result [source "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_gen_core.tcl"]
+
+exit $result
+
diff --git a/ip/fifo_generator_v7_2_0/pa_cg_migrate_project_invoke.tcl b/ip/fifo_generator_v7_2_0/pa_cg_migrate_project_invoke.tcl new file mode 100755 index 0000000..c491aad --- /dev/null +++ b/ip/fifo_generator_v7_2_0/pa_cg_migrate_project_invoke.tcl @@ -0,0 +1,25 @@ +# Tcl script generated by PlanAhead
+
+set tclUtilsPath "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl"
+
+set cgProjectPath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/coregen.cgc"
+
+set ipFile "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/fifo_2kx18.xco"
+
+set ipName "fifo_2kx18"
+
+set chains "APPLY_CURRENT_PROJECT_OPTIONS_CHAIN BATCH_CUSTOMIZE_CHAIN INSTANTIATION_TEMPLATES_CHAIN"
+
+set vlnv "xilinx.com:ip:fifo_generator:7.2"
+
+set cgPartSpec "6slx9-2tqg144"
+
+set bomFilePath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/pa_cg_bom.xml"
+
+set hdlType "Verilog"
+
+# migrate the project
+set result [source "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_migrate_project.tcl"]
+
+exit $result
+
diff --git a/ip/fifo_generator_v7_2_0/pa_cg_reconfig_core_invoke.tcl b/ip/fifo_generator_v7_2_0/pa_cg_reconfig_core_invoke.tcl new file mode 100755 index 0000000..15041a4 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/pa_cg_reconfig_core_invoke.tcl @@ -0,0 +1,21 @@ +# Tcl script generated by PlanAhead
+
+set tclUtilsPath "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl"
+
+set cgProjectPath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/coregen.cgc"
+
+set ipName "fifo_2kx18"
+
+set chains "CUSTOMIZE_CURRENT_CHAIN INSTANTIATION_TEMPLATES_CHAIN"
+
+set bomFilePath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/pa_cg_bom.xml"
+
+set cgPartSpec "6slx9-2tqg144"
+
+set hdlType "Verilog"
+
+# generate the IP
+set result [source "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_reconfig_core.tcl"]
+
+exit $result
+
diff --git a/ip/license.txt b/ip/license.txt new file mode 100755 index 0000000..6777efc --- /dev/null +++ b/ip/license.txt @@ -0,0 +1,11 @@ +The files in this directory tree are auto-generated by the Xilinx IP Core
+Generator System.
+
+The configuration of the IP embodied in these files is the expression of
+Andrew "bunnie" Huang's thoughts and these thoughts are licensed in a
+CC-BY-SA 2.0 fashion. The copyright notice is located here instead of
+in the file, since the configuration files are stored in a machine-
+manipulated format that is not suitable for insertion of copyright notices.
+
+The generation of the IP from these configurations is guided by the requirements
+of Xilinx's IP Core Generator System.
|