1 files changed, 22 insertions, 0 deletions
diff --git a/ip/clk_wiz_v3_1_0/coregen.cgp b/ip/clk_wiz_v3_1_0/coregen.cgp
new file mode 100755
index 0000000..555710a
--- /dev/null
+++ b/ip/clk_wiz_v3_1_0/coregen.cgp
@@ -0,0 +1,22 @@
+# Date: Tue Aug 09 21:35:33 2011
+
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+SET workingdirectory = ./tmp/
+
+# CRC: e7d90245