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/*******************************************************************************
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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
fifo_2kx18 YourInstanceName (
.rst(rst), // input rst
.wr_clk(wr_clk), // input wr_clk
.rd_clk(rd_clk), // input rd_clk
.din(din), // input [17 : 0] din
.wr_en(wr_en), // input wr_en
.rd_en(rd_en), // input rd_en
.dout(dout), // ouput [17 : 0] dout
.full(full), // ouput full
.empty(empty)); // ouput empty
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file fifo_2kx18.v when simulating
// the core, fifo_2kx18. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
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