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Diffstat (limited to 'ip/fifo_generator_v7_2_0/fifo_2kx18.veo')
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1 files changed, 70 insertions, 0 deletions
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.veo b/ip/fifo_generator_v7_2_0/fifo_2kx18.veo new file mode 100755 index 0000000..be52216 --- /dev/null +++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.veo @@ -0,0 +1,70 @@ +/*******************************************************************************
+* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
+* *
+* This file contains confidential and proprietary information *
+* of Xilinx, Inc. and is protected under U.S. and *
+* international copyright and other intellectual property *
+* laws. *
+* *
+* DISCLAIMER *
+* This disclaimer is not a license and does not grant any *
+* rights to the materials distributed herewith. Except as *
+* otherwise provided in a valid license issued to you by *
+* Xilinx, and to the maximum extent permitted by applicable *
+* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
+* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
+* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
+* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
+* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
+* (2) Xilinx shall not be liable (whether in contract or tort, *
+* including negligence, or under any other theory of *
+* liability) for any loss or damage of any kind or nature *
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+* special, incidental, or consequential loss or damage *
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+* possibility of the same. *
+* *
+* CRITICAL APPLICATIONS *
+* Xilinx products are not designed or intended to be fail- *
+* safe, or for use in any application requiring fail-safe *
+* performance, such as life-support or safety devices or *
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+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
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+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_2kx18 YourInstanceName (
+ .rst(rst), // input rst
+ .wr_clk(wr_clk), // input wr_clk
+ .rd_clk(rd_clk), // input rd_clk
+ .din(din), // input [17 : 0] din
+ .wr_en(wr_en), // input wr_en
+ .rd_en(rd_en), // input rd_en
+ .dout(dout), // ouput [17 : 0] dout
+ .full(full), // ouput full
+ .empty(empty)); // ouput empty
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_2kx18.v when simulating
+// the core, fifo_2kx18. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
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