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-rwxr-xr-xip/fifo_generator_v7_2_0/.lso1
-rwxr-xr-xip/fifo_generator_v7_2_0/coregen.cgc528
-rwxr-xr-xip/fifo_generator_v7_2_0/coregen.cgp22
-rwxr-xr-xip/fifo_generator_v7_2_0/coregen.log44
-rwxr-xr-xip/fifo_generator_v7_2_0/fifo_2kx18.asy41
-rwxr-xr-xip/fifo_generator_v7_2_0/fifo_2kx18.gise32
-rwxr-xr-xip/fifo_generator_v7_2_0/fifo_2kx18.ngc3
-rwxr-xr-xip/fifo_generator_v7_2_0/fifo_2kx18.v498
-rwxr-xr-xip/fifo_generator_v7_2_0/fifo_2kx18.veo70
-rwxr-xr-xip/fifo_generator_v7_2_0/fifo_2kx18.xco203
-rwxr-xr-xip/fifo_generator_v7_2_0/fifo_2kx18.xise399
-rwxr-xr-xip/fifo_generator_v7_2_0/fifo_2kx18_flist.txt12
-rwxr-xr-xip/fifo_generator_v7_2_0/fifo_2kx18_xmdf.tcl76
-rwxr-xr-xip/fifo_generator_v7_2_0/fifo_generator_readme.txt185
-rwxr-xr-xip/fifo_generator_v7_2_0/pa_cg_bom.xml39
-rwxr-xr-xip/fifo_generator_v7_2_0/pa_cg_gen_core_invoke.tcl17
-rwxr-xr-xip/fifo_generator_v7_2_0/pa_cg_migrate_project_invoke.tcl25
-rwxr-xr-xip/fifo_generator_v7_2_0/pa_cg_reconfig_core_invoke.tcl21
18 files changed, 2216 insertions, 0 deletions
diff --git a/ip/fifo_generator_v7_2_0/.lso b/ip/fifo_generator_v7_2_0/.lso
new file mode 100755
index 0000000..05eddb4
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/.lso
@@ -0,0 +1 @@
+fifo_generator_v7_2
diff --git a/ip/fifo_generator_v7_2_0/coregen.cgc b/ip/fifo_generator_v7_2_0/coregen.cgc
new file mode 100755
index 0000000..b07d8e9
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/coregen.cgc
@@ -0,0 +1,528 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" >
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>projects</spirit:library>
+ <spirit:name>coregen</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>fifo_2kx18</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="7.2" />
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">fifo_2kx18</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_HANDSHAKE_FLAG_OPTIONS_RDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WDCH">Empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DEPTH">2048</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WRCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WDCH">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DATA_WIDTH">18</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_AXIS">Full</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_HANDSHAKE_FLAG_OPTIONS_WRCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TKEEP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_BUSER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_READ_CHANNEL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WUSER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_AWUSER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_AXIS">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WACH">Full</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_AXIS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_AXIS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_AXIS">1024</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_RESET_VALUE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WACH">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXIS_TYPE">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WDCH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_FLAGS_RESET_VALUE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_WIDTH">64</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WACH">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH">2048</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE_AXI">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_HANDSHAKE_FLAG_OPTIONS_WDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RACH">1022</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_OVERFLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RDCH">Full</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WACH_TYPE">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RDCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_UNDERFLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WRCH">Full</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_TYPE_AXI">Common_Clock</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDATA">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_ENABLE_TYPE">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RDCH">1024</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WRCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_SENSE">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TUSER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WRCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DATA_WIDTH">18</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WRCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RACH">Empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WRCH">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE">2045</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RACH">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADD_NGC_CONSTRAINT_AXI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS_AXI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_AXIS">1022</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RACH_TYPE">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PIN">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WACH">1022</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_WDCH">Full</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TSTROBE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RACH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_WDCH">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_WDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_AXIS">Empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_WDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_WDCH">1024</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_AXIS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TLAST">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_AXIS">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_HANDSHAKE_FLAG_OPTIONS_RACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EXTRA_LOGIC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG_AXI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WACH">Empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_RDCH">1022</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_WRITE_CHANNEL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WDCH_TYPE">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WACH">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WRCH">1022</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_NEGATE_VALUE">2044</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_EMPTY_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_AXIS">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">Asynchronous_Reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRCH_TYPE">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DOUT_RESET">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WACH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_RDCH">Empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_AXIS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_RDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_HANDSHAKE_FLAG_OPTIONS_AXIS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_RDCH">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_FULL_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_SENSE">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE_WRCH">Empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_WACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RDCH_TYPE">FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATA_COUNTS_WRCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_NEGATE_VALUE">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_APPLICATION_TYPE_WRCH">Data_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_HANDSHAKE_FLAG_OPTIONS_WACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TREADY">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE_RACH">Full</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_ENABLE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE_WDCH">1022</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RUSER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EMBEDDED_REGISTERS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PERFORMANCE_OPTIONS">Standard_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_TYPE">AXI4_Stream</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ARUSER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TDEST">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION_RACH">Common_Clock_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_RDCH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC_RACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RESET_SYNCHRONIZATION">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR_RACH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ADDRESS_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH_RACH">16</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE_WRCH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR_RDCH">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">2kx18</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
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+ <xilinx:checkSum>0xBF5DD5B7</xilinx:checkSum>
+ <xilinx:generationId>generationid_3501100592</xilinx:generationId>
+ </xilinx:file>
+ </xilinx:fileSet>
+ <xilinx:fileSet>
+ <xilinx:name>ise_generator</xilinx:name>
+ <xilinx:file>
+ <xilinx:name>./fifo_2kx18.gise</xilinx:name>
+ <xilinx:userFileType>ignore</xilinx:userFileType>
+ <xilinx:userFileType>gise</xilinx:userFileType>
+ <xilinx:timeStamp>Tue Aug 09 21:47:10 GMT 2011</xilinx:timeStamp>
+ <xilinx:checkSum>0xAC308EE9</xilinx:checkSum>
+ <xilinx:generationId>generationid_3501100592</xilinx:generationId>
+ </xilinx:file>
+ <xilinx:file>
+ <xilinx:name>./fifo_2kx18.xise</xilinx:name>
+ <xilinx:userFileType>ignore</xilinx:userFileType>
+ <xilinx:userFileType>xise</xilinx:userFileType>
+ <xilinx:timeStamp>Tue Aug 09 21:47:10 GMT 2011</xilinx:timeStamp>
+ <xilinx:checkSum>0xC62EA0FE</xilinx:checkSum>
+ <xilinx:generationId>generationid_3501100592</xilinx:generationId>
+ </xilinx:file>
+ </xilinx:fileSet>
+ <xilinx:fileSet>
+ <xilinx:name>deliver_readme_generator</xilinx:name>
+ </xilinx:fileSet>
+ <xilinx:fileSet>
+ <xilinx:name>flist_generator</xilinx:name>
+ <xilinx:file>
+ <xilinx:name>./fifo_2kx18_flist.txt</xilinx:name>
+ <xilinx:userFileType>ignore</xilinx:userFileType>
+ <xilinx:userFileType>txtFlist</xilinx:userFileType>
+ <xilinx:userFileType>txt</xilinx:userFileType>
+ <xilinx:timeStamp>Tue Aug 09 21:47:10 GMT 2011</xilinx:timeStamp>
+ <xilinx:checkSum>0x64B4445D</xilinx:checkSum>
+ <xilinx:generationId>generationid_3501100592</xilinx:generationId>
+ </xilinx:file>
+ </xilinx:fileSet>
+ </xilinx:generationHistory>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+ <spirit:vendorExtensions>
+ <xilinx:instanceProperties>
+ <xilinx:projectOptions>
+ <xilinx:projectName>coregen</xilinx:projectName>
+ <xilinx:outputDirectory>./</xilinx:outputDirectory>
+ <xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
+ <xilinx:subWorkingDirectory>./tmp/_cg</xilinx:subWorkingDirectory>
+ </xilinx:projectOptions>
+ <xilinx:part>
+ <xilinx:device>xc6slx9</xilinx:device>
+ <xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
+ <xilinx:package>tqg144</xilinx:package>
+ <xilinx:speedGrade>-2</xilinx:speedGrade>
+ </xilinx:part>
+ <xilinx:flowOptions>
+ <xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
+ <xilinx:designEntry>Verilog</xilinx:designEntry>
+ <xilinx:asySymbol>true</xilinx:asySymbol>
+ <xilinx:flowVendor>Foundation_ISE</xilinx:flowVendor>
+ <xilinx:addPads>false</xilinx:addPads>
+ <xilinx:removeRPMs>false</xilinx:removeRPMs>
+ <xilinx:createNDF>false</xilinx:createNDF>
+ <xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
+ <xilinx:formalVerification>false</xilinx:formalVerification>
+ </xilinx:flowOptions>
+ <xilinx:simulationOptions>
+ <xilinx:simulationModel>Behavioral</xilinx:simulationModel>
+ <xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
+ <xilinx:foundationSym>false</xilinx:foundationSym>
+ </xilinx:simulationOptions>
+ </xilinx:instanceProperties>
+ </spirit:vendorExtensions>
+</spirit:design>
diff --git a/ip/fifo_generator_v7_2_0/coregen.cgp b/ip/fifo_generator_v7_2_0/coregen.cgp
new file mode 100755
index 0000000..0725064
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/coregen.cgp
@@ -0,0 +1,22 @@
+# Date: Tue Aug 09 21:31:41 2011
+
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+SET workingdirectory = ./tmp/
+
+# CRC: d3c0f20c
diff --git a/ip/fifo_generator_v7_2_0/coregen.log b/ip/fifo_generator_v7_2_0/coregen.log
new file mode 100755
index 0000000..b090d84
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/coregen.log
@@ -0,0 +1,44 @@
+CoreGen has not been configured with any user repositories.
+CoreGen has been configured with the following Xilinx repositories:
+ - 'C:\Xilinx\13.1\ISE_DS\ISE\coregen\' []
+INFO:sim:927 - Generating component instance 'fifo_2kx18' of
+ 'xilinx.com:ip:fifo_generator:7.2' from
+ 'C:\Xilinx\13.1\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\fifo_gener
+ ator_v7_2\fifo_generator_v7_2.xcd'.
+Resolving generic values...
+Initializing IP model...
+Finished initializing IP model.
+Finished resolving generic values.
+Generating IP...
+WARNING:sim:975 - You are using Fifo Generator 7.2 which has been replaced with
+ a new version. This version of the core will be removed in a future release.
+ Cores in this state are not supported.
+WARNING:sim:89 - A core named <fifo_2kx18> already exists in the output
+ directory. Output products for this core may be overwritten.
+XST: HDL Parsing
+XST: HDL Elaboration
+XST: HDL Synthesis
+XST: Advanced HDL Synthesis
+XST: Low Level Synthesis
+Generating Implementation files.
+Picked up JAVA_TOOL_OPTIONS: -Xmx2048m
+Generating NGC file.
+Finished Generation.
+Generating IP instantiation template...
+Finished generating IP instantiation template.
+Generating ASY schematic symbol...
+Initializing IP model...
+Finished initializing IP model.
+Finished generating ASY schematic symbol.
+Generating metadata file...
+Finished generating metadata file.
+Generating ISE project...
+Finished generating ISE project.Generating README file...
+Finished generating README file.
+Generating FLIST file...
+Finished FLIST file generation.
+Preparing output directory...
+Finished preparing output directory.
+Moving files to output directory...
+Finished moving files to output directory
+Saved options for project 'coregen'.
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.asy b/ip/fifo_generator_v7_2_0/fifo_2kx18.asy
new file mode 100755
index 0000000..b01eb08
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.asy
@@ -0,0 +1,41 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 fifo_2kx18
+RECTANGLE Normal 32 32 800 3712
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Normal 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Wide 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName din[17:0]
+PINATTR Polarity IN
+LINE Normal 0 304 32 304
+PIN 0 304 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 496 32 496
+PIN 0 496 LEFT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Normal 832 240 800 240
+PIN 832 240 RIGHT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Wide 832 272 800 272
+PIN 832 272 RIGHT 36
+PINATTR PinName dout[17:0]
+PINATTR Polarity OUT
+LINE Normal 832 304 800 304
+PIN 832 304 RIGHT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 832 496 800 496
+PIN 832 496 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.gise b/ip/fifo_generator_v7_2_0/fifo_2kx18.gise
new file mode 100755
index 0000000..4bcc080
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.gise
@@ -0,0 +1,32 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo_2kx18.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo_2kx18.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VEO" xil_pn:name="fifo_2kx18.veo" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.ngc b/ip/fifo_generator_v7_2_0/fifo_2kx18.ngc
new file mode 100755
index 0000000..e1c560f
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
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\ No newline at end of file
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.v b/ip/fifo_generator_v7_2_0/fifo_2kx18.v
new file mode 100755
index 0000000..2583396
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.v
@@ -0,0 +1,498 @@
+/*******************************************************************************
+* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
+* *
+* This file contains confidential and proprietary information *
+* of Xilinx, Inc. and is protected under U.S. and *
+* international copyright and other intellectual property *
+* laws. *
+* *
+* DISCLAIMER *
+* This disclaimer is not a license and does not grant any *
+* rights to the materials distributed herewith. Except as *
+* otherwise provided in a valid license issued to you by *
+* Xilinx, and to the maximum extent permitted by applicable *
+* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
+* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
+* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
+* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
+* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
+* (2) Xilinx shall not be liable (whether in contract or tort, *
+* including negligence, or under any other theory of *
+* liability) for any loss or damage of any kind or nature *
+* related to, arising under or in connection with these *
+* materials, including for any direct, or any indirect, *
+* special, incidental, or consequential loss or damage *
+* (including loss of data, profits, goodwill, or any type of *
+* loss or damage suffered as a result of any action brought *
+* by a third party) even if such damage or loss was *
+* reasonably foreseeable or Xilinx had been advised of the *
+* possibility of the same. *
+* *
+* CRITICAL APPLICATIONS *
+* Xilinx products are not designed or intended to be fail- *
+* safe, or for use in any application requiring fail-safe *
+* performance, such as life-support or safety devices or *
+* systems, Class III medical devices, nuclear facilities, *
+* applications related to the deployment of airbags, or any *
+* other applications that could lead to death, personal *
+* injury, or severe property or environmental damage *
+* (individually and collectively, "Critical *
+* Applications"). Customer assumes the sole risk and *
+* liability of any use of Xilinx products in Critical *
+* Applications, subject only to applicable laws and *
+* regulations governing limitations on product liability. *
+* *
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
+* PART OF THIS FILE AT ALL TIMES. *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_2kx18.v when simulating
+// the core, fifo_2kx18. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_2kx18(
+ rst,
+ wr_clk,
+ rd_clk,
+ din,
+ wr_en,
+ rd_en,
+ dout,
+ full,
+ empty);
+
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [17 : 0] din;
+input wr_en;
+input rd_en;
+output [17 : 0] dout;
+output full;
+output empty;
+
+// synthesis translate_off
+
+ FIFO_GENERATOR_V7_2 #(
+ .C_ADD_NGC_CONSTRAINT(0),
+ .C_APPLICATION_TYPE_AXIS(0),
+ .C_APPLICATION_TYPE_RACH(0),
+ .C_APPLICATION_TYPE_RDCH(0),
+ .C_APPLICATION_TYPE_WACH(0),
+ .C_APPLICATION_TYPE_WDCH(0),
+ .C_APPLICATION_TYPE_WRCH(0),
+ .C_AXIS_TDATA_WIDTH(64),
+ .C_AXIS_TDEST_WIDTH(4),
+ .C_AXIS_TID_WIDTH(8),
+ .C_AXIS_TKEEP_WIDTH(4),
+ .C_AXIS_TSTRB_WIDTH(4),
+ .C_AXIS_TUSER_WIDTH(4),
+ .C_AXIS_TYPE(0),
+ .C_AXI_ADDR_WIDTH(32),
+ .C_AXI_ARUSER_WIDTH(1),
+ .C_AXI_AWUSER_WIDTH(1),
+ .C_AXI_BUSER_WIDTH(1),
+ .C_AXI_DATA_WIDTH(64),
+ .C_AXI_ID_WIDTH(4),
+ .C_AXI_RUSER_WIDTH(1),
+ .C_AXI_TYPE(0),
+ .C_AXI_WUSER_WIDTH(1),
+ .C_COMMON_CLOCK(0),
+ .C_COUNT_TYPE(0),
+ .C_DATA_COUNT_WIDTH(11),
+ .C_DEFAULT_VALUE("BlankString"),
+ .C_DIN_WIDTH(18),
+ .C_DIN_WIDTH_AXIS(1),
+ .C_DIN_WIDTH_RACH(32),
+ .C_DIN_WIDTH_RDCH(64),
+ .C_DIN_WIDTH_WACH(32),
+ .C_DIN_WIDTH_WDCH(64),
+ .C_DIN_WIDTH_WRCH(2),
+ .C_DOUT_RST_VAL("0"),
+ .C_DOUT_WIDTH(18),
+ .C_ENABLE_RLOCS(0),
+ .C_ENABLE_RST_SYNC(1),
+ .C_ERROR_INJECTION_TYPE(0),
+ .C_ERROR_INJECTION_TYPE_AXIS(0),
+ .C_ERROR_INJECTION_TYPE_RACH(0),
+ .C_ERROR_INJECTION_TYPE_RDCH(0),
+ .C_ERROR_INJECTION_TYPE_WACH(0),
+ .C_ERROR_INJECTION_TYPE_WDCH(0),
+ .C_ERROR_INJECTION_TYPE_WRCH(0),
+ .C_FAMILY("spartan6"),
+ .C_FULL_FLAGS_RST_VAL(1),
+ .C_HAS_ALMOST_EMPTY(0),
+ .C_HAS_ALMOST_FULL(0),
+ .C_HAS_AXIS_TDATA(0),
+ .C_HAS_AXIS_TDEST(0),
+ .C_HAS_AXIS_TID(0),
+ .C_HAS_AXIS_TKEEP(0),
+ .C_HAS_AXIS_TLAST(0),
+ .C_HAS_AXIS_TREADY(1),
+ .C_HAS_AXIS_TSTRB(0),
+ .C_HAS_AXIS_TUSER(0),
+ .C_HAS_AXI_ARUSER(0),
+ .C_HAS_AXI_AWUSER(0),
+ .C_HAS_AXI_BUSER(0),
+ .C_HAS_AXI_RD_CHANNEL(0),
+ .C_HAS_AXI_RUSER(0),
+ .C_HAS_AXI_WR_CHANNEL(0),
+ .C_HAS_AXI_WUSER(0),
+ .C_HAS_BACKUP(0),
+ .C_HAS_DATA_COUNT(0),
+ .C_HAS_DATA_COUNTS_AXIS(0),
+ .C_HAS_DATA_COUNTS_RACH(0),
+ .C_HAS_DATA_COUNTS_RDCH(0),
+ .C_HAS_DATA_COUNTS_WACH(0),
+ .C_HAS_DATA_COUNTS_WDCH(0),
+ .C_HAS_DATA_COUNTS_WRCH(0),
+ .C_HAS_INT_CLK(0),
+ .C_HAS_MASTER_CE(0),
+ .C_HAS_MEMINIT_FILE(0),
+ .C_HAS_OVERFLOW(0),
+ .C_HAS_PROG_FLAGS_AXIS(0),
+ .C_HAS_PROG_FLAGS_RACH(0),
+ .C_HAS_PROG_FLAGS_RDCH(0),
+ .C_HAS_PROG_FLAGS_WACH(0),
+ .C_HAS_PROG_FLAGS_WDCH(0),
+ .C_HAS_PROG_FLAGS_WRCH(0),
+ .C_HAS_RD_DATA_COUNT(0),
+ .C_HAS_RD_RST(0),
+ .C_HAS_RST(1),
+ .C_HAS_SLAVE_CE(0),
+ .C_HAS_SRST(0),
+ .C_HAS_UNDERFLOW(0),
+ .C_HAS_VALID(0),
+ .C_HAS_WR_ACK(0),
+ .C_HAS_WR_DATA_COUNT(0),
+ .C_HAS_WR_RST(0),
+ .C_IMPLEMENTATION_TYPE(2),
+ .C_IMPLEMENTATION_TYPE_AXIS(1),
+ .C_IMPLEMENTATION_TYPE_RACH(1),
+ .C_IMPLEMENTATION_TYPE_RDCH(1),
+ .C_IMPLEMENTATION_TYPE_WACH(1),
+ .C_IMPLEMENTATION_TYPE_WDCH(1),
+ .C_IMPLEMENTATION_TYPE_WRCH(1),
+ .C_INIT_WR_PNTR_VAL(0),
+ .C_INTERFACE_TYPE(0),
+ .C_MEMORY_TYPE(1),
+ .C_MIF_FILE_NAME("BlankString"),
+ .C_MSGON_VAL(1),
+ .C_OPTIMIZATION_MODE(0),
+ .C_OVERFLOW_LOW(0),
+ .C_PRELOAD_LATENCY(1),
+ .C_PRELOAD_REGS(0),
+ .C_PRIM_FIFO_TYPE("2kx18"),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
+ .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
+ .C_PROG_EMPTY_TYPE(0),
+ .C_PROG_EMPTY_TYPE_AXIS(5),
+ .C_PROG_EMPTY_TYPE_RACH(5),
+ .C_PROG_EMPTY_TYPE_RDCH(5),
+ .C_PROG_EMPTY_TYPE_WACH(5),
+ .C_PROG_EMPTY_TYPE_WDCH(5),
+ .C_PROG_EMPTY_TYPE_WRCH(5),
+ .C_PROG_FULL_THRESH_ASSERT_VAL(2045),
+ .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
+ .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
+ .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
+ .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
+ .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
+ .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
+ .C_PROG_FULL_THRESH_NEGATE_VAL(2044),
+ .C_PROG_FULL_TYPE(0),
+ .C_PROG_FULL_TYPE_AXIS(5),
+ .C_PROG_FULL_TYPE_RACH(5),
+ .C_PROG_FULL_TYPE_RDCH(5),
+ .C_PROG_FULL_TYPE_WACH(5),
+ .C_PROG_FULL_TYPE_WDCH(5),
+ .C_PROG_FULL_TYPE_WRCH(5),
+ .C_RACH_TYPE(0),
+ .C_RDCH_TYPE(0),
+ .C_RD_DATA_COUNT_WIDTH(11),
+ .C_RD_DEPTH(2048),
+ .C_RD_FREQ(1),
+ .C_RD_PNTR_WIDTH(11),
+ .C_REG_SLICE_MODE_AXIS(0),
+ .C_REG_SLICE_MODE_RACH(0),
+ .C_REG_SLICE_MODE_RDCH(0),
+ .C_REG_SLICE_MODE_WACH(0),
+ .C_REG_SLICE_MODE_WDCH(0),
+ .C_REG_SLICE_MODE_WRCH(0),
+ .C_UNDERFLOW_LOW(0),
+ .C_USE_COMMON_OVERFLOW(0),
+ .C_USE_COMMON_UNDERFLOW(0),
+ .C_USE_DEFAULT_SETTINGS(0),
+ .C_USE_DOUT_RST(0),
+ .C_USE_ECC(0),
+ .C_USE_ECC_AXIS(0),
+ .C_USE_ECC_RACH(0),
+ .C_USE_ECC_RDCH(0),
+ .C_USE_ECC_WACH(0),
+ .C_USE_ECC_WDCH(0),
+ .C_USE_ECC_WRCH(0),
+ .C_USE_EMBEDDED_REG(0),
+ .C_USE_FIFO16_FLAGS(0),
+ .C_USE_FWFT_DATA_COUNT(0),
+ .C_VALID_LOW(0),
+ .C_WACH_TYPE(0),
+ .C_WDCH_TYPE(0),
+ .C_WRCH_TYPE(0),
+ .C_WR_ACK_LOW(0),
+ .C_WR_DATA_COUNT_WIDTH(11),
+ .C_WR_DEPTH(2048),
+ .C_WR_DEPTH_AXIS(1024),
+ .C_WR_DEPTH_RACH(16),
+ .C_WR_DEPTH_RDCH(1024),
+ .C_WR_DEPTH_WACH(16),
+ .C_WR_DEPTH_WDCH(1024),
+ .C_WR_DEPTH_WRCH(16),
+ .C_WR_FREQ(1),
+ .C_WR_PNTR_WIDTH(11),
+ .C_WR_PNTR_WIDTH_AXIS(10),
+ .C_WR_PNTR_WIDTH_RACH(4),
+ .C_WR_PNTR_WIDTH_RDCH(10),
+ .C_WR_PNTR_WIDTH_WACH(4),
+ .C_WR_PNTR_WIDTH_WDCH(10),
+ .C_WR_PNTR_WIDTH_WRCH(4),
+ .C_WR_RESPONSE_LATENCY(1))
+ inst (
+ .RST(rst),
+ .WR_CLK(wr_clk),
+ .RD_CLK(rd_clk),
+ .DIN(din),
+ .WR_EN(wr_en),
+ .RD_EN(rd_en),
+ .DOUT(dout),
+ .FULL(full),
+ .EMPTY(empty),
+ .BACKUP(),
+ .BACKUP_MARKER(),
+ .CLK(),
+ .SRST(),
+ .WR_RST(),
+ .RD_RST(),
+ .PROG_EMPTY_THRESH(),
+ .PROG_EMPTY_THRESH_ASSERT(),
+ .PROG_EMPTY_THRESH_NEGATE(),
+ .PROG_FULL_THRESH(),
+ .PROG_FULL_THRESH_ASSERT(),
+ .PROG_FULL_THRESH_NEGATE(),
+ .INT_CLK(),
+ .INJECTDBITERR(),
+ .INJECTSBITERR(),
+ .ALMOST_FULL(),
+ .WR_ACK(),
+ .OVERFLOW(),
+ .ALMOST_EMPTY(),
+ .VALID(),
+ .UNDERFLOW(),
+ .DATA_COUNT(),
+ .RD_DATA_COUNT(),
+ .WR_DATA_COUNT(),
+ .PROG_FULL(),
+ .PROG_EMPTY(),
+ .SBITERR(),
+ .DBITERR(),
+ .M_ACLK(),
+ .S_ACLK(),
+ .S_ARESETN(),
+ .M_ACLK_EN(),
+ .S_ACLK_EN(),
+ .S_AXI_AWID(),
+ .S_AXI_AWADDR(),
+ .S_AXI_AWLEN(),
+ .S_AXI_AWSIZE(),
+ .S_AXI_AWBURST(),
+ .S_AXI_AWLOCK(),
+ .S_AXI_AWCACHE(),
+ .S_AXI_AWPROT(),
+ .S_AXI_AWQOS(),
+ .S_AXI_AWREGION(),
+ .S_AXI_AWUSER(),
+ .S_AXI_AWVALID(),
+ .S_AXI_AWREADY(),
+ .S_AXI_WID(),
+ .S_AXI_WDATA(),
+ .S_AXI_WSTRB(),
+ .S_AXI_WLAST(),
+ .S_AXI_WUSER(),
+ .S_AXI_WVALID(),
+ .S_AXI_WREADY(),
+ .S_AXI_BID(),
+ .S_AXI_BRESP(),
+ .S_AXI_BUSER(),
+ .S_AXI_BVALID(),
+ .S_AXI_BREADY(),
+ .M_AXI_AWID(),
+ .M_AXI_AWADDR(),
+ .M_AXI_AWLEN(),
+ .M_AXI_AWSIZE(),
+ .M_AXI_AWBURST(),
+ .M_AXI_AWLOCK(),
+ .M_AXI_AWCACHE(),
+ .M_AXI_AWPROT(),
+ .M_AXI_AWQOS(),
+ .M_AXI_AWREGION(),
+ .M_AXI_AWUSER(),
+ .M_AXI_AWVALID(),
+ .M_AXI_AWREADY(),
+ .M_AXI_WID(),
+ .M_AXI_WDATA(),
+ .M_AXI_WSTRB(),
+ .M_AXI_WLAST(),
+ .M_AXI_WUSER(),
+ .M_AXI_WVALID(),
+ .M_AXI_WREADY(),
+ .M_AXI_BID(),
+ .M_AXI_BRESP(),
+ .M_AXI_BUSER(),
+ .M_AXI_BVALID(),
+ .M_AXI_BREADY(),
+ .S_AXI_ARID(),
+ .S_AXI_ARADDR(),
+ .S_AXI_ARLEN(),
+ .S_AXI_ARSIZE(),
+ .S_AXI_ARBURST(),
+ .S_AXI_ARLOCK(),
+ .S_AXI_ARCACHE(),
+ .S_AXI_ARPROT(),
+ .S_AXI_ARQOS(),
+ .S_AXI_ARREGION(),
+ .S_AXI_ARUSER(),
+ .S_AXI_ARVALID(),
+ .S_AXI_ARREADY(),
+ .S_AXI_RID(),
+ .S_AXI_RDATA(),
+ .S_AXI_RRESP(),
+ .S_AXI_RLAST(),
+ .S_AXI_RUSER(),
+ .S_AXI_RVALID(),
+ .S_AXI_RREADY(),
+ .M_AXI_ARID(),
+ .M_AXI_ARADDR(),
+ .M_AXI_ARLEN(),
+ .M_AXI_ARSIZE(),
+ .M_AXI_ARBURST(),
+ .M_AXI_ARLOCK(),
+ .M_AXI_ARCACHE(),
+ .M_AXI_ARPROT(),
+ .M_AXI_ARQOS(),
+ .M_AXI_ARREGION(),
+ .M_AXI_ARUSER(),
+ .M_AXI_ARVALID(),
+ .M_AXI_ARREADY(),
+ .M_AXI_RID(),
+ .M_AXI_RDATA(),
+ .M_AXI_RRESP(),
+ .M_AXI_RLAST(),
+ .M_AXI_RUSER(),
+ .M_AXI_RVALID(),
+ .M_AXI_RREADY(),
+ .S_AXIS_TVALID(),
+ .S_AXIS_TREADY(),
+ .S_AXIS_TDATA(),
+ .S_AXIS_TSTRB(),
+ .S_AXIS_TKEEP(),
+ .S_AXIS_TLAST(),
+ .S_AXIS_TID(),
+ .S_AXIS_TDEST(),
+ .S_AXIS_TUSER(),
+ .M_AXIS_TVALID(),
+ .M_AXIS_TREADY(),
+ .M_AXIS_TDATA(),
+ .M_AXIS_TSTRB(),
+ .M_AXIS_TKEEP(),
+ .M_AXIS_TLAST(),
+ .M_AXIS_TID(),
+ .M_AXIS_TDEST(),
+ .M_AXIS_TUSER(),
+ .AXI_AW_INJECTSBITERR(),
+ .AXI_AW_INJECTDBITERR(),
+ .AXI_AW_PROG_FULL_THRESH(),
+ .AXI_AW_PROG_EMPTY_THRESH(),
+ .AXI_AW_DATA_COUNT(),
+ .AXI_AW_WR_DATA_COUNT(),
+ .AXI_AW_RD_DATA_COUNT(),
+ .AXI_AW_SBITERR(),
+ .AXI_AW_DBITERR(),
+ .AXI_AW_OVERFLOW(),
+ .AXI_AW_UNDERFLOW(),
+ .AXI_W_INJECTSBITERR(),
+ .AXI_W_INJECTDBITERR(),
+ .AXI_W_PROG_FULL_THRESH(),
+ .AXI_W_PROG_EMPTY_THRESH(),
+ .AXI_W_DATA_COUNT(),
+ .AXI_W_WR_DATA_COUNT(),
+ .AXI_W_RD_DATA_COUNT(),
+ .AXI_W_SBITERR(),
+ .AXI_W_DBITERR(),
+ .AXI_W_OVERFLOW(),
+ .AXI_W_UNDERFLOW(),
+ .AXI_B_INJECTSBITERR(),
+ .AXI_B_INJECTDBITERR(),
+ .AXI_B_PROG_FULL_THRESH(),
+ .AXI_B_PROG_EMPTY_THRESH(),
+ .AXI_B_DATA_COUNT(),
+ .AXI_B_WR_DATA_COUNT(),
+ .AXI_B_RD_DATA_COUNT(),
+ .AXI_B_SBITERR(),
+ .AXI_B_DBITERR(),
+ .AXI_B_OVERFLOW(),
+ .AXI_B_UNDERFLOW(),
+ .AXI_AR_INJECTSBITERR(),
+ .AXI_AR_INJECTDBITERR(),
+ .AXI_AR_PROG_FULL_THRESH(),
+ .AXI_AR_PROG_EMPTY_THRESH(),
+ .AXI_AR_DATA_COUNT(),
+ .AXI_AR_WR_DATA_COUNT(),
+ .AXI_AR_RD_DATA_COUNT(),
+ .AXI_AR_SBITERR(),
+ .AXI_AR_DBITERR(),
+ .AXI_AR_OVERFLOW(),
+ .AXI_AR_UNDERFLOW(),
+ .AXI_R_INJECTSBITERR(),
+ .AXI_R_INJECTDBITERR(),
+ .AXI_R_PROG_FULL_THRESH(),
+ .AXI_R_PROG_EMPTY_THRESH(),
+ .AXI_R_DATA_COUNT(),
+ .AXI_R_WR_DATA_COUNT(),
+ .AXI_R_RD_DATA_COUNT(),
+ .AXI_R_SBITERR(),
+ .AXI_R_DBITERR(),
+ .AXI_R_OVERFLOW(),
+ .AXI_R_UNDERFLOW(),
+ .AXIS_INJECTSBITERR(),
+ .AXIS_INJECTDBITERR(),
+ .AXIS_PROG_FULL_THRESH(),
+ .AXIS_PROG_EMPTY_THRESH(),
+ .AXIS_DATA_COUNT(),
+ .AXIS_WR_DATA_COUNT(),
+ .AXIS_RD_DATA_COUNT(),
+ .AXIS_SBITERR(),
+ .AXIS_DBITERR(),
+ .AXIS_OVERFLOW(),
+ .AXIS_UNDERFLOW());
+
+
+// synthesis translate_on
+
+// XST black box declaration
+// box_type "black_box"
+// synthesis attribute box_type of fifo_2kx18 is "black_box"
+
+endmodule
+
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.veo b/ip/fifo_generator_v7_2_0/fifo_2kx18.veo
new file mode 100755
index 0000000..be52216
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.veo
@@ -0,0 +1,70 @@
+/*******************************************************************************
+* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
+* *
+* This file contains confidential and proprietary information *
+* of Xilinx, Inc. and is protected under U.S. and *
+* international copyright and other intellectual property *
+* laws. *
+* *
+* DISCLAIMER *
+* This disclaimer is not a license and does not grant any *
+* rights to the materials distributed herewith. Except as *
+* otherwise provided in a valid license issued to you by *
+* Xilinx, and to the maximum extent permitted by applicable *
+* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
+* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
+* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
+* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
+* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
+* (2) Xilinx shall not be liable (whether in contract or tort, *
+* including negligence, or under any other theory of *
+* liability) for any loss or damage of any kind or nature *
+* related to, arising under or in connection with these *
+* materials, including for any direct, or any indirect, *
+* special, incidental, or consequential loss or damage *
+* (including loss of data, profits, goodwill, or any type of *
+* loss or damage suffered as a result of any action brought *
+* by a third party) even if such damage or loss was *
+* reasonably foreseeable or Xilinx had been advised of the *
+* possibility of the same. *
+* *
+* CRITICAL APPLICATIONS *
+* Xilinx products are not designed or intended to be fail- *
+* safe, or for use in any application requiring fail-safe *
+* performance, such as life-support or safety devices or *
+* systems, Class III medical devices, nuclear facilities, *
+* applications related to the deployment of airbags, or any *
+* other applications that could lead to death, personal *
+* injury, or severe property or environmental damage *
+* (individually and collectively, "Critical *
+* Applications"). Customer assumes the sole risk and *
+* liability of any use of Xilinx products in Critical *
+* Applications, subject only to applicable laws and *
+* regulations governing limitations on product liability. *
+* *
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
+* PART OF THIS FILE AT ALL TIMES. *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_2kx18 YourInstanceName (
+ .rst(rst), // input rst
+ .wr_clk(wr_clk), // input wr_clk
+ .rd_clk(rd_clk), // input rd_clk
+ .din(din), // input [17 : 0] din
+ .wr_en(wr_en), // input wr_en
+ .rd_en(rd_en), // input rd_en
+ .dout(dout), // ouput [17 : 0] dout
+ .full(full), // ouput full
+ .empty(empty)); // ouput empty
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_2kx18.v when simulating
+// the core, fifo_2kx18. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.xco b/ip/fifo_generator_v7_2_0/fifo_2kx18.xco
new file mode 100755
index 0000000..f892af2
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.xco
@@ -0,0 +1,203 @@
+##############################################################
+#
+# Xilinx Core Generator version 13.1
+# Date: Tue Aug 09 21:46:42 2011
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 7.2
+# END Select
+# BEGIN Parameters
+CSET add_ngc_constraint_axi=false
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET aruser_width=1
+CSET awuser_width=1
+CSET axi_address_width=32
+CSET axi_data_width=64
+CSET axi_type=AXI4_Stream
+CSET axis_type=FIFO
+CSET buser_width=1
+CSET clock_enable_type=Slave_Interface_Clock_Enable
+CSET clock_type_axi=Common_Clock
+CSET component_name=fifo_2kx18
+CSET data_count=false
+CSET data_count_width=11
+CSET disable_timing_violations=false
+CSET disable_timing_violations_axi=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_assert_value_axis=1022
+CSET empty_threshold_assert_value_rach=1022
+CSET empty_threshold_assert_value_rdch=1022
+CSET empty_threshold_assert_value_wach=1022
+CSET empty_threshold_assert_value_wdch=1022
+CSET empty_threshold_assert_value_wrch=1022
+CSET empty_threshold_negate_value=3
+CSET enable_aruser=false
+CSET enable_awuser=false
+CSET enable_buser=false
+CSET enable_common_overflow=false
+CSET enable_common_underflow=false
+CSET enable_data_counts_axis=false
+CSET enable_data_counts_rach=false
+CSET enable_data_counts_rdch=false
+CSET enable_data_counts_wach=false
+CSET enable_data_counts_wdch=false
+CSET enable_data_counts_wrch=false
+CSET enable_ecc=false
+CSET enable_ecc_axis=false
+CSET enable_ecc_rach=false
+CSET enable_ecc_rdch=false
+CSET enable_ecc_wach=false
+CSET enable_ecc_wdch=false
+CSET enable_ecc_wrch=false
+CSET enable_handshake_flag_options_axis=false
+CSET enable_handshake_flag_options_rach=false
+CSET enable_handshake_flag_options_rdch=false
+CSET enable_handshake_flag_options_wach=false
+CSET enable_handshake_flag_options_wdch=false
+CSET enable_handshake_flag_options_wrch=false
+CSET enable_read_channel=false
+CSET enable_reset_synchronization=true
+CSET enable_ruser=false
+CSET enable_tdata=false
+CSET enable_tdest=false
+CSET enable_tid=false
+CSET enable_tkeep=false
+CSET enable_tlast=false
+CSET enable_tready=true
+CSET enable_tstrobe=false
+CSET enable_tuser=false
+CSET enable_write_channel=false
+CSET enable_wuser=false
+CSET fifo_application_type_axis=Data_FIFO
+CSET fifo_application_type_rach=Data_FIFO
+CSET fifo_application_type_rdch=Data_FIFO
+CSET fifo_application_type_wach=Data_FIFO
+CSET fifo_application_type_wdch=Data_FIFO
+CSET fifo_application_type_wrch=Data_FIFO
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET fifo_implementation_axis=Common_Clock_Block_RAM
+CSET fifo_implementation_rach=Common_Clock_Block_RAM
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wach=Common_Clock_Block_RAM
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=2045
+CSET full_threshold_assert_value_axis=1023
+CSET full_threshold_assert_value_rach=1023
+CSET full_threshold_assert_value_rdch=1023
+CSET full_threshold_assert_value_wach=1023
+CSET full_threshold_assert_value_wdch=1023
+CSET full_threshold_assert_value_wrch=1023
+CSET full_threshold_negate_value=2044
+CSET id_width=4
+CSET inject_dbit_error=false
+CSET inject_dbit_error_axis=false
+CSET inject_dbit_error_rach=false
+CSET inject_dbit_error_rdch=false
+CSET inject_dbit_error_wach=false
+CSET inject_dbit_error_wdch=false
+CSET inject_dbit_error_wrch=false
+CSET inject_sbit_error=false
+CSET inject_sbit_error_axis=false
+CSET inject_sbit_error_rach=false
+CSET inject_sbit_error_rdch=false
+CSET inject_sbit_error_wach=false
+CSET inject_sbit_error_wdch=false
+CSET inject_sbit_error_wrch=false
+CSET input_data_width=18
+CSET input_depth=2048
+CSET input_depth_axis=1024
+CSET input_depth_rach=16
+CSET input_depth_rdch=1024
+CSET input_depth_wach=16
+CSET input_depth_wdch=1024
+CSET input_depth_wrch=16
+CSET interface_type=Native
+CSET output_data_width=18
+CSET output_depth=2048
+CSET overflow_flag=false
+CSET overflow_flag_axi=false
+CSET overflow_sense=Active_High
+CSET overflow_sense_axi=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_axis=Empty
+CSET programmable_empty_type_rach=Empty
+CSET programmable_empty_type_rdch=Empty
+CSET programmable_empty_type_wach=Empty
+CSET programmable_empty_type_wdch=Empty
+CSET programmable_empty_type_wrch=Empty
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET programmable_full_type_axis=Full
+CSET programmable_full_type_rach=Full
+CSET programmable_full_type_rdch=Full
+CSET programmable_full_type_wach=Full
+CSET programmable_full_type_wdch=Full
+CSET programmable_full_type_wrch=Full
+CSET rach_type=FIFO
+CSET rdch_type=FIFO
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=11
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET ruser_width=1
+CSET tdata_width=64
+CSET tdest_width=4
+CSET tid_width=8
+CSET tkeep_width=4
+CSET tstrb_width=4
+CSET tuser_width=4
+CSET underflow_flag=false
+CSET underflow_flag_axi=false
+CSET underflow_sense=Active_High
+CSET underflow_sense_axi=Active_High
+CSET use_clock_enable=false
+CSET use_dout_reset=false
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET wach_type=FIFO
+CSET wdch_type=FIFO
+CSET wrch_type=FIFO
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=11
+CSET wuser_width=1
+# END Parameters
+GENERATE
+# CRC: 5a428ec2
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18.xise b/ip/fifo_generator_v7_2_0/fifo_2kx18.xise
new file mode 100755
index 0000000..284f7d3
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/fifo_2kx18.xise
@@ -0,0 +1,399 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="fifo_2kx18.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ </file>
+ <file xil_pn:name="fifo_2kx18.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+ <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+ <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+ <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
+ <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
+ <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
+ <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
+ <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+ <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
+ <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
+ <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+ <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+ <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+ <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+ <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
+ <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+ <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
+ <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Module|fifo_2kx18" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="fifo_2kx18.ngc" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo_2kx18" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+ <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
+ <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+ <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output File Name" xil_pn:value="fifo_2kx18" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
+ <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
+ <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+ <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="fifo_2kx18_map.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="fifo_2kx18_timesim.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="fifo_2kx18_synthesis.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="fifo_2kx18_translate.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+ <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+ <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+ <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+ <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+ <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+ <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+ <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+ <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
+ <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo_2kx18" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-08-10T05:47:09" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C3C07357CF834C1EB043358346420692" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18_flist.txt b/ip/fifo_generator_v7_2_0/fifo_2kx18_flist.txt
new file mode 100755
index 0000000..fb00e08
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/fifo_2kx18_flist.txt
@@ -0,0 +1,12 @@
+# Output products list for <fifo_2kx18>
+fifo_2kx18.asy
+fifo_2kx18.gise
+fifo_2kx18.ngc
+fifo_2kx18.v
+fifo_2kx18.veo
+fifo_2kx18.xco
+fifo_2kx18.xise
+fifo_2kx18_flist.txt
+fifo_2kx18_xmdf.tcl
+fifo_generator_readme.txt
+fifo_generator_ug175.pdf
diff --git a/ip/fifo_generator_v7_2_0/fifo_2kx18_xmdf.tcl b/ip/fifo_generator_v7_2_0/fifo_2kx18_xmdf.tcl
new file mode 100755
index 0000000..629d396
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/fifo_2kx18_xmdf.tcl
@@ -0,0 +1,76 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_2kx18_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_2kx18_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_2kx18_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_2kx18
+}
+# ::fifo_2kx18_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_2kx18_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_2kx18.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_2kx18.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_2kx18.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_2kx18.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_2kx18.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_2kx18_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_2kx18
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/ip/fifo_generator_v7_2_0/fifo_generator_readme.txt b/ip/fifo_generator_v7_2_0/fifo_generator_readme.txt
new file mode 100755
index 0000000..3cc2fc3
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/fifo_generator_readme.txt
@@ -0,0 +1,185 @@
+ Core Name: Xilinx LogiCORE FIFO Generator
+ Version: 7.2
+ Release Date: September 21, 2010
+
+
+================================================================================
+
+This document contains the following sections:
+
+1. Introduction
+2. New Features
+3. Supported Devices
+4. Resolved Issues
+5. Known Issues
+6. Technical Support
+7. Core Release History
+8. Legal Disclaimer
+
+================================================================================
+
+1. INTRODUCTION
+
+For the most recent updates to the IP installation instructions for this core,
+please go to:
+
+ http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+
+For software requirements, please go to the "Software Requirements" link on that page.
+
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v7.2
+solution. For the latest core updates, see the product page at:
+
+ http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+
+2. NEW FEATURES
+
+ - AXI4 (AXI4-Stream, AXI4 and AXI4-Lite) Support (Spartan-6 and Virtex-6 devices only)
+ - ISE 12.3 software support
+
+3. SUPPORTED DEVICES
+
+ The following device families are supported by the core for this release.
+
+ - Virtex-6 XC CXT/LXT/SXT/HXT
+ - Virtex-6 XQ LXT/SXT
+ - Virtex-6 -1L XC LXT/SXT
+
+ - Spartan-6 XC LX/LXT
+ - Spartan-6 XA
+ - Spartan-6 XQ LX/LXT
+ - Spartan-6 -1L XC LX
+
+ - Virtex-5 XC LX/LXT/SXT/TXT/FXT
+ - Virtex-5 XQ LX/ LXT/SXT/FXT
+
+ - Virtex-4 XC LX/SX/FX
+ - Virtex-4 XQ LX/SX/FX
+ - Virtex-4 XQR LX/SX/FX
+
+ - Spartan-3 XC
+ - Spartan-3 XA
+ - Spartan-3A XC 3A / 3A DSP / 3AN DSP
+ - Spartan-3A XA 3A / 3A DSP
+ - Spartan-3E XC
+ - Spartan-3E XA
+
+4. RESOLVED ISSUES
+
+ - In the FIFO Generator GUI, navigation buttons at the bottom are not accessible unless the screen resolution
+ is set to 1600x1200 or 1900x1200.
+ - CR 568630
+
+ - The FIFO Generator GUI does not generate the core if the depth is reduced after the data count option is selected.
+ - CR 570314
+
+5. KNOWN ISSUES
+
+ The following are known issues for v7.2 of this core at time of release:
+
+ - In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+ into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
+ page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+ - CR 467240
+ - AR 31379
+
+ - The FIFO Generator GUI does not generate the core if the Family is Spartan-6, and FIFO Implementation Type is
+ either Common or Independent Clock Block RAM, and the depth is 64K and the width is 36.
+ - CR 570041
+ - AR 37201
+
+ The most recent information, including known issues, workarounds, and
+ resolutions for this version is provided in the IP Release Notes User Guide
+ located at
+
+ www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+
+6. TECHNICAL SUPPORT
+
+ To obtain technical support, create a WebCase at www.xilinx.com/support.
+ Questions are routed to a team with expertise using this product.
+
+ Xilinx provides technical support for use of this product when used
+ according to the guidelines described in the core documentation, and
+ cannot guarantee timing, functionality, or support of this product for
+ designs that do not follow specified guidelines.
+
+
+7. CORE RELEASE HISTORY
+
+Date By Version Description
+================================================================================
+09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
+07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
+06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
+04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
+12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
+08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
+05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
+04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
+================================================================================
+
+8. Legal Disclaimer
+
+ (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
+
+ This file contains confidential and proprietary information
+ of Xilinx, Inc. and is protected under U.S. and
+ international copyright and other intellectual property
+ laws.
+
+ DISCLAIMER
+ This disclaimer is not a license and does not grant any
+ rights to the materials distributed herewith. Except as
+ otherwise provided in a valid license issued to you by
+ Xilinx, and to the maximum extent permitted by applicable
+ law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+ (2) Xilinx shall not be liable (whether in contract or tort,
+ including negligence, or under any other theory of
+ liability) for any loss or damage of any kind or nature
+ related to, arising under or in connection with these
+ materials, including for any direct, or any indirect,
+ special, incidental, or consequential loss or damage
+ (including loss of data, profits, goodwill, or any type of
+ loss or damage suffered as a result of any action brought
+ by a third party) even if such damage or loss was
+ reasonably foreseeable or Xilinx had been advised of the
+ possibility of the same.
+
+ CRITICAL APPLICATIONS
+ Xilinx products are not designed or intended to be fail-
+ safe, or for use in any application requiring fail-safe
+ performance, such as life-support or safety devices or
+ systems, Class III medical devices, nuclear facilities,
+ applications related to the deployment of airbags, or any
+ other applications that could lead to death, personal
+ injury, or severe property or environmental damage
+ (individually and collectively, "Critical
+ Applications"). Customer assumes the sole risk and
+ liability of any use of Xilinx products in Critical
+ Applications, subject only to applicable laws and
+ regulations governing limitations on product liability.
+
+ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+ PART OF THIS FILE AT ALL TIMES.
diff --git a/ip/fifo_generator_v7_2_0/pa_cg_bom.xml b/ip/fifo_generator_v7_2_0/pa_cg_bom.xml
new file mode 100755
index 0000000..ec972e8
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/pa_cg_bom.xml
@@ -0,0 +1,39 @@
+<?xml version="1.0"?>
+<BillOfMaterials Version="1" Minor="2">
+ <IPInstance name="fifo_2kx18">
+ <FileSets>
+ <FileSet generator="model_parameter_resolution_generator">
+ <File name="./model_parameter_resolution_generator.xlog" type="ignore" timestamp="Tue Aug 09 21:47:10 GMT 2011" checksum="0xFFFFFFFF"></File>
+ </FileSet>
+ <FileSet generator="ip_xco_generator">
+ <File name="./fifo_2kx18.xco" type="xco" timestamp="Tue Aug 09 21:46:42 GMT 2011" checksum="0x200AB8B2"></File>
+ </FileSet>
+ <FileSet generator="ngc_netlist_generator">
+ <File name="./fifo_2kx18.ngc" type="ngc" timestamp="Tue Aug 09 21:47:05 GMT 2011" checksum="0x80830D9F"></File>
+ <File name="./fifo_2kx18.v" type="verilog" timestamp="Tue Aug 09 21:46:58 GMT 2011" checksum="0x6726F87E"></File>
+ <File name="./fifo_2kx18.veo" type="veo" timestamp="Tue Aug 09 21:46:58 GMT 2011" checksum="0x368CEE5B"></File>
+ <File name="./fifo_generator_readme.txt" type="txt" timestamp="Tue Aug 09 21:46:58 GMT 2011" checksum="0x8C1691E3"></File>
+ <File name="./fifo_generator_ug175.pdf" type="pdf" timestamp="Tue Aug 09 21:46:58 GMT 2011" checksum="0x7B853EF8"></File>
+ </FileSet>
+ <FileSet generator="instantiation_template_generator">
+ <File name="./fifo_2kx18.veo" type="veo" timestamp="Tue Aug 09 21:47:05 GMT 2011" checksum="0x368CEE5B"></File>
+ </FileSet>
+ <FileSet generator="asy_generator">
+ <File name="./fifo_2kx18.asy" type="asy" timestamp="Tue Aug 09 21:47:08 GMT 2011" checksum="0x903A7B6F"></File>
+ </FileSet>
+ <FileSet generator="xmdf_generator">
+ <File name="./fifo_2kx18_xmdf.tcl" type="tclXmdf" timestamp="Tue Aug 09 21:47:08 GMT 2011" checksum="0xBF5DD5B7"></File>
+ </FileSet>
+ <FileSet generator="ise_generator">
+ <File name="./fifo_2kx18.gise" type="ignore" timestamp="Tue Aug 09 21:47:10 GMT 2011" checksum="0xAC308EE9"></File>
+ <File name="./fifo_2kx18.xise" type="ignore" timestamp="Tue Aug 09 21:47:10 GMT 2011" checksum="0xC62EA0FE"></File>
+ </FileSet>
+ <FileSet generator="deliver_readme_generator">
+ <File name="./deliver_readme_generator.xlog" type="ignore" timestamp="Tue Aug 09 21:47:10 GMT 2011" checksum="0xFFFFFFFF"></File>
+ </FileSet>
+ <FileSet generator="flist_generator">
+ <File name="./fifo_2kx18_flist.txt" type="ignore" timestamp="Tue Aug 09 21:47:10 GMT 2011" checksum="0x64B4445D"></File>
+ </FileSet>
+ </FileSets>
+ </IPInstance>
+</BillOfMaterials>
diff --git a/ip/fifo_generator_v7_2_0/pa_cg_gen_core_invoke.tcl b/ip/fifo_generator_v7_2_0/pa_cg_gen_core_invoke.tcl
new file mode 100755
index 0000000..1863d00
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/pa_cg_gen_core_invoke.tcl
@@ -0,0 +1,17 @@
+# Tcl script generated by PlanAhead
+
+set tclUtilsPath "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl"
+
+set cgProjectPath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/coregen.cgc"
+
+set ipName "fifo_2kx18"
+
+set chains "GENERATE_CHAIN"
+
+set bomFilePath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/pa_cg_bom.xml"
+
+# generate the IP
+set result [source "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_gen_core.tcl"]
+
+exit $result
+
diff --git a/ip/fifo_generator_v7_2_0/pa_cg_migrate_project_invoke.tcl b/ip/fifo_generator_v7_2_0/pa_cg_migrate_project_invoke.tcl
new file mode 100755
index 0000000..c491aad
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/pa_cg_migrate_project_invoke.tcl
@@ -0,0 +1,25 @@
+# Tcl script generated by PlanAhead
+
+set tclUtilsPath "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl"
+
+set cgProjectPath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/coregen.cgc"
+
+set ipFile "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/fifo_2kx18.xco"
+
+set ipName "fifo_2kx18"
+
+set chains "APPLY_CURRENT_PROJECT_OPTIONS_CHAIN BATCH_CUSTOMIZE_CHAIN INSTANTIATION_TEMPLATES_CHAIN"
+
+set vlnv "xilinx.com:ip:fifo_generator:7.2"
+
+set cgPartSpec "6slx9-2tqg144"
+
+set bomFilePath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/pa_cg_bom.xml"
+
+set hdlType "Verilog"
+
+# migrate the project
+set result [source "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_migrate_project.tcl"]
+
+exit $result
+
diff --git a/ip/fifo_generator_v7_2_0/pa_cg_reconfig_core_invoke.tcl b/ip/fifo_generator_v7_2_0/pa_cg_reconfig_core_invoke.tcl
new file mode 100755
index 0000000..15041a4
--- /dev/null
+++ b/ip/fifo_generator_v7_2_0/pa_cg_reconfig_core_invoke.tcl
@@ -0,0 +1,21 @@
+# Tcl script generated by PlanAhead
+
+set tclUtilsPath "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl"
+
+set cgProjectPath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/coregen.cgc"
+
+set ipName "fifo_2kx18"
+
+set chains "CUSTOMIZE_CURRENT_CHAIN INSTANTIATION_TEMPLATES_CHAIN"
+
+set bomFilePath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/pa_cg_bom.xml"
+
+set cgPartSpec "6slx9-2tqg144"
+
+set hdlType "Verilog"
+
+# generate the IP
+set result [source "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_reconfig_core.tcl"]
+
+exit $result
+
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-21 19:12:10 +0000