diff options
Diffstat (limited to 'ip/fifo_generator_v7_2_0/pa_cg_migrate_project_invoke.tcl')
| -rwxr-xr-x | ip/fifo_generator_v7_2_0/pa_cg_migrate_project_invoke.tcl | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/ip/fifo_generator_v7_2_0/pa_cg_migrate_project_invoke.tcl b/ip/fifo_generator_v7_2_0/pa_cg_migrate_project_invoke.tcl new file mode 100755 index 0000000..c491aad --- /dev/null +++ b/ip/fifo_generator_v7_2_0/pa_cg_migrate_project_invoke.tcl @@ -0,0 +1,25 @@ +# Tcl script generated by PlanAhead
+
+set tclUtilsPath "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl"
+
+set cgProjectPath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/coregen.cgc"
+
+set ipFile "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/fifo_2kx18.xco"
+
+set ipName "fifo_2kx18"
+
+set chains "APPLY_CURRENT_PROJECT_OPTIONS_CHAIN BATCH_CUSTOMIZE_CHAIN INSTANTIATION_TEMPLATES_CHAIN"
+
+set vlnv "xilinx.com:ip:fifo_generator:7.2"
+
+set cgPartSpec "6slx9-2tqg144"
+
+set bomFilePath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/fifo_generator_v7_2_0/pa_cg_bom.xml"
+
+set hdlType "Verilog"
+
+# migrate the project
+set result [source "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_migrate_project.tcl"]
+
+exit $result
+
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