path: root/ip/clk_wiz_v3_1_0/clkgendcm_720p60hz.ejp

Encore.Project.ProjectDir = C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/tmp/_cg
Encore.Project.ElaborationDir = C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/tmp/_cg
Encore.Project.TmpDir = C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/tmp/_cg
Encore.Project.Path = C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/tmp/_cg
Encore.Project.FlowVendor = Other
Encore.Project.VhdlSim = false
Encore.Project.VerilogSim = true
Encore.Project.XDevice = xc6slx9
Encore.Project.XDeviceFamily = spartan6
Encore.Project.XSpeedGrade = -2
Encore.Project.XPackage = tqg144

c_use_clkout1_bar = 0
c_use_clkout2_bar = 0
c_use_clkout3_bar = 0
c_use_clkout4_bar = 0
component_name = clkgendcm_720p60hz
c_platform = nt64
c_use_freq_synth = 1
c_use_phase_alignment = 0
c_use_min_o_jitter = 0
c_use_max_i_jitter = 0
c_use_dyn_phase_shift = 0
c_use_inclk_switchover = 0
c_use_dyn_reconfig = 0
c_use_spread_spectrum = 0
c_primtype_sel = DCM_CLKGEN
c_use_clk_valid = 0
c_prim_in_freq = 26
c_in_freq_units = Units_MHz
c_secondary_in_freq = 100.000
c_feedback_source = FDBK_AUTO
c_prim_source = No_buffer
c_secondary_source = Single_ended_clock_capable_pin
c_clkfb_in_signaling = SINGLE
c_use_reset = 1
c_use_locked = 1
c_use_inclk_stopped = 0
c_use_power_down = 0
c_use_status = 0
c_use_freeze = 0
c_num_out_clks = 1
c_clkout1_drives = BUFG
c_clkout2_drives = BUFG
c_clkout3_drives = BUFG
c_clkout4_drives = BUFG
c_clkout5_drives = BUFG
c_clkout6_drives = BUFG
c_clkout7_drives = BUFG
c_inclk_sum_row0 = Input Clock   Input Freq (MHz)   Input Jitter (UI)
c_inclk_sum_row1 = primary              26            0.010
c_inclk_sum_row2 = no secondary input clock 
c_outclk_sum_row0a = Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
c_outclk_sum_row0b = Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
c_outclk_sum_row1 = CLK_OUT1    74.287      0.000       N/A      200.000        N/A
c_outclk_sum_row2 = no CLK_OUT2 output
c_outclk_sum_row3 = no CLK_OUT3 output 
c_outclk_sum_row4 = no CLK_OUT4 output
c_outclk_sum_row5 = no CLK_OUT5 output
c_outclk_sum_row6 = no CLK_OUT6 output
c_outclk_sum_row7 = no CLK_OUT7 output 
c_clkout1_requested_out_freq = 74.285
c_clkout2_requested_out_freq = 100.000
c_clkout3_requested_out_freq = 100.000
c_clkout4_requested_out_freq = 100.000
c_clkout5_requested_out_freq = 100.000
c_clkout6_requested_out_freq = 100.000
c_clkout7_requested_out_freq = 100.000
c_clkout1_requested_phase = 0.000
c_clkout2_requested_phase = 0.000
c_clkout3_requested_phase = 0.000
c_clkout4_requested_phase = 0.000
c_clkout5_requested_phase = 0.000
c_clkout6_requested_phase = 0.000
c_clkout7_requested_phase = 0.000
c_clkout1_requested_duty_cycle = 50.0
c_clkout2_requested_duty_cycle = 50.0
c_clkout3_requested_duty_cycle = 50.0
c_clkout4_requested_duty_cycle = 50.0
c_clkout5_requested_duty_cycle = 50.0
c_clkout6_requested_duty_cycle = 50.0
c_clkout7_requested_duty_cycle = 50.0
c_clkout1_out_freq = 74.287
c_clkout2_out_freq = N/A
c_clkout3_out_freq = N/A
c_clkout4_out_freq = N/A
c_clkout5_out_freq = N/A
c_clkout6_out_freq = N/A
c_clkout7_out_freq = N/A
c_clkout1_phase = 0.000
c_clkout2_phase = N/A
c_clkout3_phase = N/A
c_clkout4_phase = N/A
c_clkout5_phase = N/A
c_clkout6_phase = N/A
c_clkout7_phase = N/A
c_clkout1_duty_cycle = N/A
c_clkout2_duty_cycle = N/A
c_clkout3_duty_cycle = N/A
c_clkout4_duty_cycle = N/A
c_clkout5_duty_cycle = N/A
c_clkout6_duty_cycle = N/A
c_clkout7_duty_cycle = N/A
c_mmcm_notes = None
c_mmcm_bandwidth = OPTIMIZED
c_mmcm_clkfbout_mult_f = 4.000
c_mmcm_clkin1_period = 10.000
c_mmcm_clkin2_period = 10.000
c_mmcm_clkout4_cascade = FALSE
c_mmcm_clock_hold = FALSE
c_mmcm_compensation = ZHOLD
c_mmcm_divclk_divide = 1
c_mmcm_ref_jitter1 = 0.010
c_mmcm_ref_jitter2 = 0.010
c_mmcm_startup_wait = FALSE
c_mmcm_clkout0_divide_f = 4.000
c_mmcm_clkout1_divide = 1
c_mmcm_clkout2_divide = 1
c_mmcm_clkout3_divide = 1
c_mmcm_clkout4_divide = 1
c_mmcm_clkout5_divide = 1
c_mmcm_clkout6_divide = 1
c_mmcm_clkout0_duty_cycle = 0.500
c_mmcm_clkout1_duty_cycle = 0.500
c_mmcm_clkout2_duty_cycle = 0.500
c_mmcm_clkout3_duty_cycle = 0.500
c_mmcm_clkout4_duty_cycle = 0.500
c_mmcm_clkout5_duty_cycle = 0.500
c_mmcm_clkout6_duty_cycle = 0.500
c_mmcm_clkfbout_phase = 0.000
c_mmcm_clkout0_phase = 0.000
c_mmcm_clkout1_phase = 0.000
c_mmcm_clkout2_phase = 0.000
c_mmcm_clkout3_phase = 0.000
c_mmcm_clkout4_phase = 0.000
c_mmcm_clkout5_phase = 0.000
c_mmcm_clkout6_phase = 0.000
c_mmcm_clkfbout_use_fine_ps = FALSE
c_mmcm_clkout0_use_fine_ps = FALSE
c_mmcm_clkout1_use_fine_ps = FALSE
c_mmcm_clkout2_use_fine_ps = FALSE
c_mmcm_clkout3_use_fine_ps = FALSE
c_mmcm_clkout4_use_fine_ps = FALSE
c_mmcm_clkout5_use_fine_ps = FALSE
c_mmcm_clkout6_use_fine_ps = FALSE
c_pll_notes = None
c_pll_bandwidth = OPTIMIZED
c_pll_clk_feedback = CLKFBOUT
c_pll_clkfbout_mult = 4
c_pll_clkin_period = 10.000
c_pll_compensation = INTERNAL
c_pll_divclk_divide = 1
c_pll_ref_jitter = 0.010
c_pll_clkout0_divide = 1
c_pll_clkout1_divide = 1
c_pll_clkout2_divide = 1
c_pll_clkout3_divide = 1
c_pll_clkout4_divide = 1
c_pll_clkout5_divide = 1
c_pll_clkout0_duty_cycle = 0.500
c_pll_clkout1_duty_cycle = 0.500
c_pll_clkout2_duty_cycle = 0.500
c_pll_clkout3_duty_cycle = 0.500
c_pll_clkout4_duty_cycle = 0.500
c_pll_clkout5_duty_cycle = 0.500
c_pll_clkfbout_phase = 0.000
c_pll_clkout0_phase = 0.000
c_pll_clkout1_phase = 0.000
c_pll_clkout2_phase = 0.000
c_pll_clkout3_phase = 0.000
c_pll_clkout4_phase = 0.000
c_pll_clkout5_phase = 0.000
c_dcm_notes = None
c_dcm_clkdv_divide = 2.000
c_dcm_clkfx_divide = 1
c_dcm_clkfx_multiply = 4
c_dcm_clkin_divide_by_2 = FALSE
c_dcm_clkin_period = 10.000
c_dcm_clkout_phase_shift = NONE
c_dcm_clk_feedback = 1X
c_dcm_clk_feedback_port = CLKOUT1
c_dcm_deskew_adjust = SYSTEM_SYNCHRONOUS
c_dcm_phase_shift = 0
c_dcm_startup_wait = FALSE
c_dcm_clk_out1_port = CLK0
c_dcm_clk_out2_port = NONE
c_dcm_clk_out3_port = NONE
c_dcm_clk_out4_port = NONE
c_dcm_clk_out5_port = NONE
c_dcm_clk_out6_port = NONE
c_dcm_clkgen_notes = 720p60hzclocksource
c_dcm_clkgen_clkfxdv_divide = 2
c_dcm_clkgen_clkfx_divide = 7
c_dcm_clkgen_clkfx_multiply = 20
c_dcm_clkgen_dfs_bandwidth = OPTIMIZED
c_dcm_clkgen_prog_md_bandwidth = OPTIMIZED
c_dcm_clkgen_clkin_period = 38.461
c_dcm_clkgen_clkfx_md_max = 0.000
c_dcm_clkgen_spread_spectrum = NONE
c_dcm_clkgen_startup_wait = FALSE
c_dcm_clkgen_clk_out1_port = CLKFX
c_dcm_clkgen_clk_out2_port = NONE
c_dcm_clkgen_clk_out3_port = NONE
c_clock_mgr_type = MANUAL
c_override_mmcm = 0
c_override_pll = 0
c_override_dcm = 0
c_override_dcm_clkgen = 1
c_dcm_pll_cascade = NONE
c_primary_port = CLK_IN1
c_secondary_port = CLK_IN2
c_clk_out1_port = CLK_OUT1
c_clk_out2_port = CLK_OUT2
c_clk_out3_port = CLK_OUT3
c_clk_out4_port = CLK_OUT4
c_clk_out5_port = CLK_OUT5
c_clk_out6_port = CLK_OUT6
c_clk_out7_port = CLK_OUT7
c_reset_port = RESET
c_locked_port = LOCKED
c_clkfb_in_port = CLKFB_IN
c_clkfb_in_p_port = CLKFB_IN_P
c_clkfb_in_n_port = CLKFB_IN_N
c_clkfb_out_port = CLKFB_OUT
c_clkfb_out_p_port = CLKFB_OUT_P
c_clkfb_out_n_port = CLKFB_OUT_N
c_power_down_port = POWER_DOWN
c_daddr_port = DADDR
c_dclk_port = DCLK
c_drdy_port = DRDY
c_dwe_port = DWE
c_din_port = DIN
c_dout_port = DOUT
c_den_port = DEN
c_psclk_port = PSCLK
c_psen_port = PSEN
c_psincdec_port = PSINCDEC
c_psdone_port = PSDONE
c_clk_valid_port = CLK_VALID
c_status_port = STATUS
c_clk_in_sel_port = CLK_IN_SEL
c_input_clk_stopped_port = INPUT_CLK_STOPPED
c_clkin1_jitter_ps = 384.61
c_clkin2_jitter_ps = 100.0
ComponentName = clkgendcm_720p60hz