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# Tcl script generated by PlanAhead
set tclUtilsPath "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_utils.tcl"
set cgProjectPath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/coregen.cgc"
set ipName "clk_wiz_v3_1_0"
set vlnv "xilinx.com:ip:clk_wiz:3.1"
set cgPartSpec "6slx9-2tqg144"
set bomFilePath "C:/largework/fpga/hdmi/release1/release1.srcs/sources_1/ip/clk_wiz_v3_1_0/pa_cg_bom.xml"
set hdlType "Verilog"
set chains "CUSTOMIZE_CHAIN INSTANTIATION_TEMPLATES_CHAIN"
# configure the IP
set result [source "C:/Xilinx/13.1/ISE_DS/PlanAhead/scripts/pa_cg_config_core.tcl"]
exit $result
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