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* add concept of 'board' for seperate ucfs and top level modulesbryan newbold2013-10-045-24/+34
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* add autoimpact target (pre-select bitfile)bryan newbold2013-10-041-0/+3
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* generic timingan targetbryan newbold2013-10-041-0/+3
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* backport improvements from SNG projectbryan newbold2013-10-042-3/+8
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* changed build-commits to have one argumentAndrew J Meyer2013-08-191-3/+9
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* added build commits scriptAndrew J Meyer2013-08-191-0/+31
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* typo: pre-par .ncd file for partial_timing analysisbryan newbold2013-06-271-1/+1
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* parameterize unconstrained timing analysisbryan newbold2013-06-271-2/+3
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* commit an .xco as an example of stripped project metadatabryan newbold2013-06-271-0/+76
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* a better minimalist project, including a timing constraintbryan newbold2013-06-272-31/+39
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* fix bugs with trce and parbryan newbold2013-06-271-4/+4
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* break out synth_effort as a variablebryan newbold2013-06-271-2/+3
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* fix potential problem with old etwr targetbryan newbold2013-06-271-1/+1
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* add planahead, fpga_editor, and timing targetsbryan newbold2013-06-271-13/+31
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* very minor style tweaks from downstream reposbryan newbold2013-06-193-2/+3
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* don't re-coregen after every little Makefile tweakbryan newbold2013-06-192-1/+4
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* proper Makefile syntax; device-specific; mcs bitwidthbryan newbold2013-06-193-16/+32
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* be more explicit about listing .v filesbryan newbold2013-06-061-0/+3
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* BUGSbryan newbold2013-06-051-0/+1
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* add 'make lint' verilog-build command; requires verilatorbryan newbold2013-06-051-1/+4
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* README: fix typo.Marti Bolivar2013-04-261-1/+1
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* update README, comments, .xise project filebryan newbold2013-04-263-12/+56
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* update with bnewbold's changesbryan newbold2013-03-273-76/+68
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* initial colorization stuffbryan newbold2013-03-272-1/+105
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* compile in multiple tb-modules (this might slow things down for you)bryan newbold2013-03-211-2/+6
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* add .ucf file referencebryan newbold2013-03-211-1/+1
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* isim in the background; hackisly fix depsbryan newbold2013-03-201-4/+4
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* fix 'main' in tb.vbryan newbold2013-03-201-1/+1
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* fixes to simulatebryan newbold2013-03-201-8/+6
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* Corrects comments (clock is 200MHz, not 100MHz) and removed incorrect clock ↵jesstherobot2013-03-201-7/+1
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* 'main', not 'project' top module by defaultbryan newbold2013-03-142-3/+3
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* fix ise project pointersbryan newbold2013-03-142-10/+20
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* improvementsbryan newbold2013-03-145-37/+54
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* update README; gitignore ./buildbryan newbold2013-03-132-15/+24
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* some simulation stuffbryan newbold2013-03-133-3/+45
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* move stuff around; backupbryan newbold2013-03-1310-15/+389
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* basic synthesis version of makefilebryan newbold2013-03-139-56/+238
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* add basic gitignorebryan newbold2013-03-104-34/+53
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* added the base filesAndrew J Meyer2013-03-0612-0/+235
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* Initial checkin and readmeAndrew J Meyer2013-03-061-0/+34
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