add concept of 'board' for seperate ucfs and top level modules

5 files changed, 34 insertions, 24 deletions

diff --git a/Makefile b/Makefile
index 20e992a..8bdf2d2 100644
--- a/Makefile
+++ b/Makefile
@@ -5,19 +5,27 @@ top_module := main
 vendor := xilinx
 
 # This is the chipset from the Xilinx SP605 dev board
+board := sp605
 family := spartan6
 device := xc6slx45t
 speedgrade := -3
 device_package := fgg484
-part := $(device)$(speedgrade)-$(device_package)
 
+# This is the chipset for the Xess Xula 2 dev board
+#board := xula2
+#family := spartan6
+#device := XC6SLX25
+#speedgrade := -2
+#device_package := ft256
+
+part := $(device)$(speedgrade)-$(device_package)
 
 # is this build host 64 or 32 bits?
 hostbits := 64
 iseenv := /opt/Xilinx/14.3/ISE_DS/
 
 # list all .v files explicitly with vfiles (no hdl/*.v business)
-vfiles := hdl/project.v
+vfiles := hdl/$(top_module)_$(board).v
 #vfiles += hdl/yours.v
 
 # can only specify a single test bench file here (for now)
diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk
index 538aad1..bc67686 100644
--- a/contrib/xilinx.mk
+++ b/contrib/xilinx.mk
@@ -6,26 +6,27 @@
 #
 # TODO: update these listings
 #
-#   variable	description
-#   ----------  -------------
-#   project	project name (top level module should match this name)
-#   top_module  top level module of the project
-#   libdir	path to library directory
-#   libs	library modules used
-#   vfiles	all local .v files
+#   variable      description
+#   ----------    -------------
+#   board         board target short-name
+#   project       project name (top level module should match this name)
+#   top_module    top level module of the project
+#   libdir        path to library directory
+#   libs          library modules used
+#   vfiles        all local .v files
 #   xilinx_cores  all local .xco files
-#   vendor      vendor of FPGA (xilinx, altera, etc.)
-#   family      FPGA device family (spartan3e) 
-#   part        FPGA part name (xc4vfx12-10-sf363)
-#   flashsize   size of flash for mcs file (16384)
-#   optfile     (optional) xst extra opttions file to put in .scr
-#   map_opts    (optional) options to give to map
-#   par_opts    (optional) options to give to par
-#   intstyle    (optional) intstyle option to all tools
+#   vendor        vendor of FPGA (xilinx, altera, etc.)
+#   family        FPGA device family (spartan3e) 
+#   part          FPGA part name (xc4vfx12-10-sf363)
+#   flashsize     size of flash for mcs file (16384)
+#   optfile       (optional) xst extra opttions file to put in .scr
+#   map_opts      (optional) options to give to map
+#   par_opts      (optional) options to give to par
+#   intstyle      (optional) intstyle option to all tools
 #
-#   files 		description
-#   ----------  	------------
-#   $(project).ucf	ucf file
+#   files         description
+#   ----------    ------------
+#   $(board).ucf  ucf file
 #
 # Library modules should have a modules.mk in their root directory,
 # namely $(libdir)/<libname>/module.mk, that simply adds to the vfiles
@@ -145,9 +146,9 @@ build/$(project).ncd: build/$(project).ngd
 	bash -c "$(xil_env); \
 	map $(intstyle) $(map_opts) $$smartguide $(project).ngd $(multithreading) $(colorize)"
 
-build/$(project).ngd: build/$(project).ngc $(project).ucf $(project).bmm
+build/$(project).ngd: build/$(project).ngc $(board).ucf $(board).bmm
 	@bash -c "$(xil_env); \
-	ngdbuild $(intstyle) $(project).ngc -bm ../$(project).bmm -sd ../cores -uc ../$(project).ucf -aul $(colorize)"
+	ngdbuild $(intstyle) $(project).ngc -bm ../$(board).bmm -sd ../cores -uc ../$(board).ucf -aul $(colorize)"
 
 build/$(project).ngc: $(vfiles) $(local_corengcs) build/$(project).scr build/$(project).prj
 	@bash -c "rm build/$(project).scr; make build/$(project).scr"
@@ -240,10 +241,10 @@ timingan:
 	@bash -c "$(xil_env); timingan &"
 
 partial_timing: build/$(project)_post_map.twr
-	@bash -c "$(xil_env); timingan -ucf ../$(project).ucf $(project).ncd $(project).pcf $(project)_post_map.twx &"
+	@bash -c "$(xil_env); timingan -ucf ../$(board).ucf $(project).ncd $(project).pcf $(project)_post_map.twx &"
 
 final_timing: build/$(project)_post_par.twr
-	@bash -c "$(xil_env); timingan -ucf ../$(project).ucf $(project)_par.ncd $(project).pcf $(project)_post_par.twx &"
+	@bash -c "$(xil_env); timingan -ucf ../$(board).ucf $(project)_par.ncd $(project).pcf $(project)_post_par.twx &"
 
 lint:
 	verilator --lint-only -Wall -I./hdl -I./cores -Wall $(top_module)
diff --git a/hdl/project.v b/hdl/main_sp605.v
index 1b4f9f2..1b4f9f2 100644
--- a/hdl/project.v
+++ b/hdl/main_sp605.v
diff --git a/sp605.bmm b/sp605.bmm
new file mode 100644
index 0000000..c915ec8
--- /dev/null
+++ b/sp605.bmm
@@ -0,0 +1 @@
+// Empty file; this is a "Block Ram Memory Map"
diff --git a/project.ucf b/sp605.ucf
index 2dba99f..2dba99f 100755..100644
--- a/project.ucf
+++ b/sp605.ucf