From 1ad824a33038856ae9a61379b4f78f1f6e888fe8 Mon Sep 17 00:00:00 2001 From: bryan newbold Date: Fri, 4 Oct 2013 21:46:17 -0400 Subject: add concept of 'board' for seperate ucfs and top level modules --- Makefile | 12 ++++++++++-- contrib/xilinx.mk | 45 +++++++++++++++++++++++---------------------- hdl/main_sp605.v | 31 +++++++++++++++++++++++++++++++ hdl/project.v | 31 ------------------------------- project.ucf | 18 ------------------ sp605.bmm | 1 + sp605.ucf | 18 ++++++++++++++++++ 7 files changed, 83 insertions(+), 73 deletions(-) create mode 100644 hdl/main_sp605.v delete mode 100644 hdl/project.v delete mode 100755 project.ucf create mode 100644 sp605.bmm create mode 100644 sp605.ucf diff --git a/Makefile b/Makefile index 20e992a..8bdf2d2 100644 --- a/Makefile +++ b/Makefile @@ -5,19 +5,27 @@ top_module := main vendor := xilinx # This is the chipset from the Xilinx SP605 dev board +board := sp605 family := spartan6 device := xc6slx45t speedgrade := -3 device_package := fgg484 -part := $(device)$(speedgrade)-$(device_package) +# This is the chipset for the Xess Xula 2 dev board +#board := xula2 +#family := spartan6 +#device := XC6SLX25 +#speedgrade := -2 +#device_package := ft256 + +part := $(device)$(speedgrade)-$(device_package) # is this build host 64 or 32 bits? hostbits := 64 iseenv := /opt/Xilinx/14.3/ISE_DS/ # list all .v files explicitly with vfiles (no hdl/*.v business) -vfiles := hdl/project.v +vfiles := hdl/$(top_module)_$(board).v #vfiles += hdl/yours.v # can only specify a single test bench file here (for now) diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk index 538aad1..bc67686 100644 --- a/contrib/xilinx.mk +++ b/contrib/xilinx.mk @@ -6,26 +6,27 @@ # # TODO: update these listings # -# variable description -# ---------- ------------- -# project project name (top level module should match this name) -# top_module top level module of the project -# libdir path to library directory -# libs library modules used -# vfiles all local .v files +# variable description +# ---------- ------------- +# board board target short-name +# project project name (top level module should match this name) +# top_module top level module of the project +# libdir path to library directory +# libs library modules used +# vfiles all local .v files # xilinx_cores all local .xco files -# vendor vendor of FPGA (xilinx, altera, etc.) -# family FPGA device family (spartan3e) -# part FPGA part name (xc4vfx12-10-sf363) -# flashsize size of flash for mcs file (16384) -# optfile (optional) xst extra opttions file to put in .scr -# map_opts (optional) options to give to map -# par_opts (optional) options to give to par -# intstyle (optional) intstyle option to all tools +# vendor vendor of FPGA (xilinx, altera, etc.) +# family FPGA device family (spartan3e) +# part FPGA part name (xc4vfx12-10-sf363) +# flashsize size of flash for mcs file (16384) +# optfile (optional) xst extra opttions file to put in .scr +# map_opts (optional) options to give to map +# par_opts (optional) options to give to par +# intstyle (optional) intstyle option to all tools # -# files description -# ---------- ------------ -# $(project).ucf ucf file +# files description +# ---------- ------------ +# $(board).ucf ucf file # # Library modules should have a modules.mk in their root directory, # namely $(libdir)//module.mk, that simply adds to the vfiles @@ -145,9 +146,9 @@ build/$(project).ncd: build/$(project).ngd bash -c "$(xil_env); \ map $(intstyle) $(map_opts) $$smartguide $(project).ngd $(multithreading) $(colorize)" -build/$(project).ngd: build/$(project).ngc $(project).ucf $(project).bmm +build/$(project).ngd: build/$(project).ngc $(board).ucf $(board).bmm @bash -c "$(xil_env); \ - ngdbuild $(intstyle) $(project).ngc -bm ../$(project).bmm -sd ../cores -uc ../$(project).ucf -aul $(colorize)" + ngdbuild $(intstyle) $(project).ngc -bm ../$(board).bmm -sd ../cores -uc ../$(board).ucf -aul $(colorize)" build/$(project).ngc: $(vfiles) $(local_corengcs) build/$(project).scr build/$(project).prj @bash -c "rm build/$(project).scr; make build/$(project).scr" @@ -240,10 +241,10 @@ timingan: @bash -c "$(xil_env); timingan &" partial_timing: build/$(project)_post_map.twr - @bash -c "$(xil_env); timingan -ucf ../$(project).ucf $(project).ncd $(project).pcf $(project)_post_map.twx &" + @bash -c "$(xil_env); timingan -ucf ../$(board).ucf $(project).ncd $(project).pcf $(project)_post_map.twx &" final_timing: build/$(project)_post_par.twr - @bash -c "$(xil_env); timingan -ucf ../$(project).ucf $(project)_par.ncd $(project).pcf $(project)_post_par.twx &" + @bash -c "$(xil_env); timingan -ucf ../$(board).ucf $(project)_par.ncd $(project).pcf $(project)_post_par.twx &" lint: verilator --lint-only -Wall -I./hdl -I./cores -Wall $(top_module) diff --git a/hdl/main_sp605.v b/hdl/main_sp605.v new file mode 100644 index 0000000..1b4f9f2 --- /dev/null +++ b/hdl/main_sp605.v @@ -0,0 +1,31 @@ +// very minimal example top-level module + +module main ( + output reg [3:0] gpio_led, + input wire [3:0] gpio_switch, + input wire SYSTEMCLOCK, + input wire PUSH_BUTTON_RESET_RAW // this is active low + ); + + wire reset; + assign reset = !PUSH_BUTTON_RESET_RAW; + + reg [25:0] throb_counter = 0; + + always @(posedge SYSTEMCLOCK) begin + if (reset) begin + gpio_led <= 7'b1111; + throb_counter <= 26'd0; + end else begin + gpio_led[1:0] <= gpio_switch[1:0]; + gpio_led[2] <= gpio_switch[2] || gpio_switch[3]; + if (throb_counter >= 26'd50_000_000) begin + gpio_led[3] <= !gpio_led[3]; + throb_counter <= 26'd0; + end else begin + throb_counter <= throb_counter + 26'd1; + end + end + end + +endmodule diff --git a/hdl/project.v b/hdl/project.v deleted file mode 100644 index 1b4f9f2..0000000 --- a/hdl/project.v +++ /dev/null @@ -1,31 +0,0 @@ -// very minimal example top-level module - -module main ( - output reg [3:0] gpio_led, - input wire [3:0] gpio_switch, - input wire SYSTEMCLOCK, - input wire PUSH_BUTTON_RESET_RAW // this is active low - ); - - wire reset; - assign reset = !PUSH_BUTTON_RESET_RAW; - - reg [25:0] throb_counter = 0; - - always @(posedge SYSTEMCLOCK) begin - if (reset) begin - gpio_led <= 7'b1111; - throb_counter <= 26'd0; - end else begin - gpio_led[1:0] <= gpio_switch[1:0]; - gpio_led[2] <= gpio_switch[2] || gpio_switch[3]; - if (throb_counter >= 26'd50_000_000) begin - gpio_led[3] <= !gpio_led[3]; - throb_counter <= 26'd0; - end else begin - throb_counter <= throb_counter + 26'd1; - end - end - end - -endmodule diff --git a/project.ucf b/project.ucf deleted file mode 100755 index 2dba99f..0000000 --- a/project.ucf +++ /dev/null @@ -1,18 +0,0 @@ - -#200MHz clock -NET "SYSTEMCLOCK" LOC = K21; -NET "SYSTEMCLOCK" TNM_NET = "SYSTEMCLOCK"; -TIMESPEC "TS_SYSTEMCLOCK" = PERIOD "SYSTEMCLOCK" 5 ns HIGH 50%; - -NET "PUSH_BUTTON_RESET_RAW" LOC = F3; - -NET "gpio_switch<0>" LOC = C18; -NET "gpio_switch<1>" LOC = Y6; -NET "gpio_switch<2>" LOC = W6; -NET "gpio_switch<3>" LOC = E4; - -NET "gpio_led<0>" LOC = D17; -NET "gpio_led<1>" LOC = AB4; -NET "gpio_led<2>" LOC = D21; -NET "gpio_led<3>" LOC = W15; - diff --git a/sp605.bmm b/sp605.bmm new file mode 100644 index 0000000..c915ec8 --- /dev/null +++ b/sp605.bmm @@ -0,0 +1 @@ +// Empty file; this is a "Block Ram Memory Map" diff --git a/sp605.ucf b/sp605.ucf new file mode 100644 index 0000000..2dba99f --- /dev/null +++ b/sp605.ucf @@ -0,0 +1,18 @@ + +#200MHz clock +NET "SYSTEMCLOCK" LOC = K21; +NET "SYSTEMCLOCK" TNM_NET = "SYSTEMCLOCK"; +TIMESPEC "TS_SYSTEMCLOCK" = PERIOD "SYSTEMCLOCK" 5 ns HIGH 50%; + +NET "PUSH_BUTTON_RESET_RAW" LOC = F3; + +NET "gpio_switch<0>" LOC = C18; +NET "gpio_switch<1>" LOC = Y6; +NET "gpio_switch<2>" LOC = W6; +NET "gpio_switch<3>" LOC = E4; + +NET "gpio_led<0>" LOC = D17; +NET "gpio_led<1>" LOC = AB4; +NET "gpio_led<2>" LOC = D21; +NET "gpio_led<3>" LOC = W15; + -- cgit v1.2.3