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| author | bryan newbold <bnewbold@leaflabs.com> | 2013-06-05 16:56:49 -0400 |
|---|---|---|
| committer | bryan newbold <bnewbold@leaflabs.com> | 2013-06-05 16:58:08 -0400 |
| commit | a52e389e01d17331c5d0e11bccfa64a354089114 (patch) | |
| tree | 5c475e4f6708158845b3a8128f5782df64db4157 | |
| parent | 57773a6b428d691c7c009af6cc8dfe447c026023 (diff) | |
| download | basic-hdl-template-a52e389e01d17331c5d0e11bccfa64a354089114.tar.gz basic-hdl-template-a52e389e01d17331c5d0e11bccfa64a354089114.zip | |
add 'make lint' verilog-build command; requires verilator
| -rw-r--r-- | contrib/xilinx.mk | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk index e6bbf8a..89bd465 100644 --- a/contrib/xilinx.mk +++ b/contrib/xilinx.mk @@ -67,7 +67,7 @@ local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc))) vfiles += $(foreach core,$(xilinx_cores),$(core:.xco=.v)) tbmods = $(foreach tbm,$(tbfiles),unenclib.`basename $(tbm) .v`) -.PHONY: default xilinx_cores clean twr etwr ise isim simulate coregen impact ldimpact +.PHONY: default xilinx_cores clean twr etwr ise isim simulate coregen impact ldimpact lint default: build/$(project).bit build/$(project).mcs xilinx_cores: $(corengcs) twr: $(project).twr @@ -214,6 +214,9 @@ ise: @mkdir -p build @bash -c "$(xil_env); cd ..; XIL_MAP_LOCWARN=0 ise $(project).xise &" +lint: + verilator --lint-only -Wall -I./hdl -I./cores -Wall $(top_module) + clean: clean_synth clean_sim rm -rf iseconfig |