basic synthesis version of makefile

9 files changed, 238 insertions, 56 deletions

diff --git a/.gitignore b/.gitignore
index 86a0f82..f1906a2 100644
--- a/.gitignore
+++ b/.gitignore
@@ -25,23 +25,38 @@ par_usage_statistics.html
 *.xpi
 *.xwbt
 *.xrpt
-synth_project/netlist.lst
-synth_project/*_pad.csv
-synth_project/*_pad.txt
-synth_project/*_summary.xml
-synth_project/*_usage.xml
-synth_project/*_xst.xrpt
-synth_project/*.ngm
-synth_project/*.ngr
-synth_project/usage_statistics_webtalk.html
-synth_project/xst/
+netlist.lst
+*_pad.csv
+*_pad.txt
+*_summary.xml
+*_usage.xml
+*_xst.xrpt
+*.ngm
+*.ngr
+xst/
 usage_statistics_webtalk.html
 webtalk.log
 xlnx_auto_0_xdb
-testbench/fuse.log
-testbench/isim.log
-testbench/isim.wdb
-testbench/fuse.xmsgs
-testbench/fuseRelaunch.cmd
-testbench/isim.wdb
-testbench/isim/
+*.log
+isim.wdb
+*.xmsgs
+fuseRelaunch.cmd
+isim.wdb
+isim/
+dump.vcd
+simulation/
+*_envsettings.html
+*_summary.html
+*.cmd_log
+*.bin
+webtalk_pn.xml
+*.xreport
+*.syr
+*.twr
+*.twx
+*.srp
+*.cfi
+*.mcs
+*.prm
+*.psr
+*.scr
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..e595d9c
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,11 @@
+project = project
+vendor = xilinx
+family = spartan3s
+part = xc3s1000-4ft256
+top_module = project
+
+iseenvfile = /opt/Xilinx/14.3/ISE_DS/settings64.sh
+
+vfiles = ./hdl/project.v
+
+include ./contrib/xilinx.mk
diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk
new file mode 100644
index 0000000..c03f4c3
--- /dev/null
+++ b/contrib/xilinx.mk
@@ -0,0 +1,181 @@
+# This file came from excamera's build example.
+#
+# The top level module should define the variables below then include
+# this file.  The files listed should be in the same directory as the
+# Makefile.  
+#
+#   variable	description
+#   ----------  -------------
+#   project	project name (top level module should match this name)
+#   top_module  top level module of the project
+#   libdir	path to library directory
+#   libs	library modules used
+#   vfiles	all local .v files
+#   xilinx_cores  all local .xco files
+#   vendor      vendor of FPGA (xilinx, altera, etc.)
+#   family      FPGA device family (spartan3e) 
+#   part        FPGA part name (xc4vfx12-10-sf363)
+#   flashsize   size of flash for mcs file (16384)
+#   optfile     (optional) xst extra opttions file to put in .scr
+#   map_opts    (optional) options to give to map
+#   par_opts    (optional) options to give to par
+#   intstyle    (optional) intstyle option to all tools
+#
+#   files 		description
+#   ----------  	------------
+#   $(project).ucf	ucf file
+#
+# Library modules should have a modules.mk in their root directory,
+# namely $(libdir)/<libname>/module.mk, that simply adds to the vfiles
+# and xilinx_cores variable.
+#
+# all the .xco files listed in xilinx_cores will be generated with core, with
+# the resulting .v and .ngc files placed back in the same directory as
+# the .xco file.
+#
+# TODO: .xco files are device dependant, should use a template based system
+#
+# NOTE: DO NOT edit this file to change settings; instead edit Makefile
+
+coregen_work_dir ?= ./coregen-tmp
+map_opts ?= -timing -ol high -detail -pr b -register_duplication -w
+par_opts ?= -ol high
+iseenvfile?= /opt/Xilinx/14.3/ISE_DS
+xil_env ?= cd ./build; source $(iseenvfile) > /dev/null
+flashsize ?= 8192
+
+libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs)) 
+mkfiles = Makefile $(libmks) contrib/xilinx.mk
+include $(libmks)
+
+corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc))
+local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc)))
+vfiles += $(foreach core,$(xilinx_cores),$(core:.xco=.v))
+junk += $(local_corengcs)
+
+.PHONY: default xilinx_cores clean twr etwr ise isim
+default: build/$(project).bit build/$(project).mcs
+xilinx_cores: $(corengcs)
+twr: $(project).twr
+etwr: $(project)_err.twr
+
+define cp_template
+$(2): $(1)
+	cp $(1) $(2)
+endef
+$(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc)))))
+
+%.ngc %.v: %.xco
+	@echo "=== rebuilding $@"
+	if [ -d $(coregen_work_dir) ]; then \
+		rm -rf $(coregen_work_dir)/*; \
+	else \
+		mkdir -p $(coregen_work_dir); \
+	fi
+	cd $(coregen_work_dir); \
+	bash -c "$(xil_env); \
+	coregen -b $$OLDPWD/$<; \
+	cd -
+	xcodir=`dirname $<`; \
+	basename=`basename $< .xco`; \
+	if [ ! -r $(coregen_work_dir/$$basename.ngc) ]; then \
+		echo "'$@' wasn't created."; \
+		exit 1; \
+	else \
+		cp $(coregen_work_dir)/$$basename.v $(coregen_work_dir)/$$basename.ngc $$xcodir; \
+	fi"
+junk += $(coregen_work_dir)
+
+date = $(shell date +%F-%H-%M)
+
+# some common junk
+junk += *.xrpt
+junk += _xmsgs
+
+programming_files: build/$(project).bit build/$(project).mcs
+	mkdir -p $@/$(date)
+	mkdir -p $@/latest
+	for x in .bit .mcs .cfi _bd.bmm; do cp $(project)$$x $@/$(date)/$(project)$$x; cp $(project)$$x $@/latest/$(project)$$x; done
+	bash -c "$(xil_env); xst -help | head -1 | sed 's/^/#/' | cat - build/$(project).scr > $@/$(date)/$(project).scr"
+
+build/$(project).mcs: build/$(project).bit
+	bash -c "$(xil_env); promgen -w -s $(flashsize) -p mcs -o $(project).mcs -u 0 $(project).bit"
+junk += $(project).mcs $(project).cfi $(project).prm
+
+build/$(project).bit: build/$(project)_par.ncd
+	bash -c "$(xil_env); \
+	bitgen $(intstyle) -g DriveDone:yes -g StartupClk:Cclk -w $(project)_par.ncd $(project).bit"
+junk += $(project).bgn $(project).bit $(project).drc $(project)_bd.bmm
+
+
+build/$(project)_par.ncd: build/$(project).ncd
+	bash -c "$(xil_env); \
+	if par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd; then \
+		:; \
+	else \
+		$(MAKE) etwr; \
+	fi "
+junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad 
+junk += $(project)_par_pad.csv $(project)_par_pad.txt 
+junk += $(project)_par.grf $(project)_par.ptwx
+junk += $(project)_par.unroutes $(project)_par.xpi
+
+build/$(project).ncd: build/$(project).ngd
+	if [ -r $(project)_par.ncd ]; then \
+		cp $(project)_par.ncd smartguide.ncd; \
+		smartguide="-smartguide smartguide.ncd"; \
+	else \
+		smartguide=""; \
+	fi; \
+	bash -c "$(xil_env); \
+	map $(intstyle) $(map_opts) $$smartguide $(project).ngd "
+junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map
+junk += smartguide.ncd $(project).psr 
+junk += $(project)_summary.xml $(project)_usage.xml
+
+build/$(project).ngd: build/$(project).ngc $(project).ucf $(project).bmm
+	bash -c "$(xil_env); \
+	ngdbuild $(intstyle) $(project).ngc -bm ../$(project).bmm"
+junk += $(project).ngd $(project).bld
+
+build/$(project).ngc: $(vfiles) $(local_corengcs) build/$(project).scr build/$(project).prj
+	bash -c "$(xil_env); xst $(intstyle) -ifn $(project).scr"
+junk += xlnx_auto* build/$(top_module).lso $(project).srp 
+junk += netlist.lst xst $(project).ngc
+
+build/$(project).prj: $(vfiles) $(mkfiles)
+	for src in $(vfiles); do echo "verilog work ../$$src" >> $(project).tmpprj; done
+	sort -u $(project).tmpprj > $@
+	rm -f $(project).tmpprj
+junk += $(project).prj
+
+optfile += $(wildcard $(project).opt)
+top_module ?= $(project)
+build/$(project).scr: $(optfile) $(mkfiles) ./contrib/xilinx.opt
+	mkdir -p build
+	echo "run" > $@
+	echo "-p $(part)" >> $@
+	echo "-top $(top_module)" >> $@
+	echo "-ifn $(project).prj" >> $@
+	echo "-ofn $(project).ngc" >> $@
+	cat ./contrib/xilinx.opt $(optfile) >> $@
+junk += $(project).scr
+
+build/$(project).post_map.twr: build/$(project).ncd
+	bash -c "$(xil_env); trce -e 10 $< $(project).pcf -o $@"
+junk += $(project).post_map.twr $(project).post_map.twx smartpreview.twr
+
+build/$(project).twr: build/$(project)_par.ncd
+	bash -c "$(xil_env); trce $< $(project).pcf -o $(project).twr"
+junk += $(project).twr $(project).twx smartpreview.twr
+
+build/$(project)_err.twr: build/$(project)_par.ncd
+	bash -c "$(xil_env); trce -e 10 $< $(project).pcf -o $(project)_err.twr"
+junk += $(project)_err.twr $(project)_err.twx
+
+.gitignore: $(mkfiles)
+	echo programming_files $(junk) | sed 's, ,\n,g' > .gitignore
+
+clean::
+	rm -rf $(junk)
+	cd build; rm -rf $(junk)
diff --git a/synth_project/project.xst b/contrib/xilinx.opt
index 9a29456..7fe9d8b 100644
--- a/synth_project/project.xst
+++ b/contrib/xilinx.opt
@@ -1,47 +1,36 @@
-set -tmpdir "./xst/projnav.tmp"
-set -xsthdpdir "./xst"
-run
--ifn project.prj
 -ifmt mixed
--ofn project
 -ofmt NGC
--p xc6slx45t-3-fgg484
--top project
--lso project.lso
--opt_mode Speed
+-opt_mode speed
 -opt_level 1
--power NO
 -iuc NO
--netlist_hierarchy rebuilt
--rtlview Yes
+-keep_hierarchy no
+-netlist_hierarchy as_optimized
+-rtlview no
 -glob_opt AllClockNets
--read_cores YES
--write_timing_constraints YES
+-read_cores yes
+-write_timing_constraints NO
 -cross_clock_analysis NO
 -hierarchy_separator /
 -bus_delimiter <>
 -case maintain
 -slice_utilization_ratio 100
 -bram_utilization_ratio 100
--dsp_utilization_ratio 100
--lc auto
--reduce_control_sets auto
--fsm_extract YES -fsm_encoding Auto
+#-dsp_utilization_ratio 100
 -safe_implementation No
+-fsm_extract YES
+-fsm_encoding Auto
 -fsm_style lut
 -ram_extract Yes
 -ram_style Auto
 -rom_extract Yes
--shreg_extract YES
 -rom_style Auto
+-shreg_extract YES
 -auto_bram_packing NO
 -resource_sharing YES
 -async_to_sync NO
--use_dsp48 auto
-# use NO for making NGC's and YES for making bitstreams
+#-use_dsp48 auto
 -iobuf YES
--max_fanout 100000
--bufg 32
+-max_fanout 500
 -register_duplication YES
 -register_balancing No
 -optimize_primitives NO
@@ -50,4 +39,4 @@ run
 -use_sync_reset Auto
 -iob auto
 -equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
\ No newline at end of file
+-slice_utilization_ratio_maxmargin 5
diff --git a/project.bmm b/project.bmm
new file mode 100644
index 0000000..c915ec8
--- /dev/null
+++ b/project.bmm
@@ -0,0 +1 @@
+// Empty file; this is a "Block Ram Memory Map"
diff --git a/synth_project/project.ucf b/project.ucf
index 322c05a..322c05a 100755
--- a/synth_project/project.ucf
+++ b/project.ucf
diff --git a/synth_project/make.sh b/synth_project/make.sh
deleted file mode 100755
index 807eba5..0000000
--- a/synth_project/make.sh
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/bin/sh -e
-
-TOP_NAME=project
-
-# ensure directory is created
-./xst/projnav.tmp/
-
-xst -ifn $TOP_NAME.xst
-ngdbuild $TOP_NAME.ngc -verbose
-map -pr b -w -detail $TOP_NAME.ngd
-par -w $TOP_NAME $TOP_NAME.ncd
-bitgen -w $TOP_NAME.ncd
-
diff --git a/synth_project/project.lso b/synth_project/project.lso
deleted file mode 100755
index a340c10..0000000
--- a/synth_project/project.lso
+++ /dev/null
@@ -1 +0,0 @@
-work
\ No newline at end of file
diff --git a/synth_project/project.prj b/synth_project/project.prj
deleted file mode 100644
index 3262aa0..0000000
--- a/synth_project/project.prj
+++ /dev/null
@@ -1 +0,0 @@
- verilog work ../hdl/project.v