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| author | bryan newbold <bnewbold@leaflabs.com> | 2013-03-20 11:53:23 -0400 |
|---|---|---|
| committer | bryan newbold <bnewbold@leaflabs.com> | 2013-03-20 11:53:32 -0400 |
| commit | 485eb6746b4d9a797f11bfaccf5c4331dc3f9718 (patch) | |
| tree | a4d52b9b90a653cefa23d611ec202a3bb0945ea5 | |
| parent | 7935ed6b728c16825006a175d5438a74393d81c4 (diff) | |
| download | basic-hdl-template-485eb6746b4d9a797f11bfaccf5c4331dc3f9718.tar.gz basic-hdl-template-485eb6746b4d9a797f11bfaccf5c4331dc3f9718.zip | |
fixes to simulate
| -rw-r--r-- | contrib/xilinx.mk | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk index b492a9c..3693e17 100644 --- a/contrib/xilinx.mk +++ b/contrib/xilinx.mk @@ -190,16 +190,14 @@ junk += $(project)_err.twr $(project)_err.twx echo programming_files $(junk) | sed 's, ,\n,g' > .gitignore tb/simulate_isim.prj: $(tbfiles) - rm $@ - for f in $(vfiles) - do - echo "verilog unenclib ../$(f)" >> $@ + rm -f $@ + for f in $(vfiles); do \ + echo "verilog unenclib ../$$f" >> $@; \ done - for f in $(tbfiles) - do - echo "verilog unenclib ../$(f)" >> $@ + for f in $(tbfiles); do \ + echo "verilog unenclib ../$$f" >> $@; \ done - echo "verilog unenclib ../$(iseenv)/ISE/verilog/src/glbl.v" >> $@ + echo "verilog unenclib $(iseenv)/ISE/verilog/src/glbl.v" >> $@ tb/isim: tb/simulate_isim.prj bash -c "$(sim_env); cd ../tb/; vlogcomp -prj simulate_isim.prj" |