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| author | bryan newbold <bnewbold@leaflabs.com> | 2013-03-14 13:11:23 -0400 |
|---|---|---|
| committer | bryan newbold <bnewbold@leaflabs.com> | 2013-03-14 13:11:23 -0400 |
| commit | eef34f2975ddb40d0aaedd7a0182111c22db47cf (patch) | |
| tree | 6c1dcf32ebd5b46ccefc723a0071cd54077510ce | |
| parent | ceaa7d984a85e7c4a43ffca62e9fb557e3f52d1a (diff) | |
| download | basic-hdl-template-eef34f2975ddb40d0aaedd7a0182111c22db47cf.tar.gz basic-hdl-template-eef34f2975ddb40d0aaedd7a0182111c22db47cf.zip | |
'main', not 'project' top module by default
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | hdl/project.v | 4 |
2 files changed, 3 insertions, 3 deletions
@@ -1,5 +1,5 @@ project = project -top_module = project +top_module = main vendor = xilinx # This is the chipset from the Xilinx SP605 dev board diff --git a/hdl/project.v b/hdl/project.v index 753597b..9e382a5 100644 --- a/hdl/project.v +++ b/hdl/project.v @@ -1,4 +1,4 @@ -module project +module main ( output wire LED_output_0, output wire LED_output_1, @@ -23,4 +23,4 @@ module project assign LED_output_5 = 1'b0; assign LED_output_6 = 1'b0; -endmodule
\ No newline at end of file +endmodule |