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-rw-r--r--Makefile2
-rw-r--r--hdl/project.v4
2 files changed, 3 insertions, 3 deletions
diff --git a/Makefile b/Makefile
index 0fd1347..3b12d98 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
project = project
-top_module = project
+top_module = main
vendor = xilinx
# This is the chipset from the Xilinx SP605 dev board
diff --git a/hdl/project.v b/hdl/project.v
index 753597b..9e382a5 100644
--- a/hdl/project.v
+++ b/hdl/project.v
@@ -1,4 +1,4 @@
-module project
+module main
(
output wire LED_output_0,
output wire LED_output_1,
@@ -23,4 +23,4 @@ module project
assign LED_output_5 = 1'b0;
assign LED_output_6 = 1'b0;
-endmodule \ No newline at end of file
+endmodule