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* add 'make lint' verilog-build command; requires verilatorbryan newbold2013-06-051-1/+4
* README: fix typo.Marti Bolivar2013-04-261-1/+1
* update README, comments, .xise project filebryan newbold2013-04-263-12/+56
* update with bnewbold's changesbryan newbold2013-03-273-76/+68
* initial colorization stuffbryan newbold2013-03-272-1/+105
* compile in multiple tb-modules (this might slow things down for you)bryan newbold2013-03-211-2/+6
* add .ucf file referencebryan newbold2013-03-211-1/+1
* isim in the background; hackisly fix depsbryan newbold2013-03-201-4/+4
* fix 'main' in tb.vbryan newbold2013-03-201-1/+1
* fixes to simulatebryan newbold2013-03-201-8/+6
* Corrects comments (clock is 200MHz, not 100MHz) and removed incorrect clock t...jesstherobot2013-03-201-7/+1
* 'main', not 'project' top module by defaultbryan newbold2013-03-142-3/+3
* fix ise project pointersbryan newbold2013-03-142-10/+20
* improvementsbryan newbold2013-03-145-37/+54
* update README; gitignore ./buildbryan newbold2013-03-132-15/+24
* some simulation stuffbryan newbold2013-03-133-3/+45
* move stuff around; backupbryan newbold2013-03-1310-15/+389
* basic synthesis version of makefilebryan newbold2013-03-139-56/+238
* add basic gitignorebryan newbold2013-03-104-34/+53
* added the base filesAndrew J Meyer2013-03-0612-0/+235
* Initial checkin and readmeAndrew J Meyer2013-03-061-0/+34