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* add a "complicated" Makefile for testingbryan newbold2013-11-122-0/+113
| | | | Also the corresponding top-level module (for Xula2)
* hack fix for bug with include orderingbryan newbold2013-11-125-16/+22
| | | | | | There seems to be a problem with the default target being overriden when a board-specific file is included before xilinx.mk. Workaround is to include targets last.
* reorder contrib/xilinx.mk; re-instate ./bitfile/bryan newbold2013-11-121-16/+25
| | | | | Bitfiles, timing reports, and par netlists now get saved in ./bitfiles/ for every rebuild (determined by bitfile rebuild).
* clean up cleaning (heh)bryan newbold2013-11-121-3/+13
| | | | | This commit fixes an old problem where coregen files get wiped by a 'clean'. To completely clear out coregen'd stuff, now use 'cleanall'
* fix typos revealed by going through QUICK_STARTbryan newbold2013-11-123-3/+10
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* stick some basic comments into aj's build-commits.shbryan newbold2013-11-121-1/+7
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* Part 3 of refactoring template files into ./contribbryan newbold2013-11-124-43/+129
| | | | Docs!
* Part 2 of refactoring template files into ./contribbryan newbold2013-11-122-58/+99
| | | | | | | This commit moves Makefile to Makefile.example. Projects using this template must now explicitly move this file to Makefile and edit it. Effectively BROKEN without Part 3, which documents this change.
* Part 1 of refactoring template files into ./contribbryan newbold2013-11-1215-87/+173
| | | | | | | | BROKEN without later parts (documentation and Makefile updates) This commit moves and deletes a lot of Xula2 and SP605 files around. It also includes a large cleanup of xilinx.mk
* minor cleanup of lint targetbryan newbold2013-11-121-1/+1
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* fold BUGS into TODO.templatebryan newbold2013-11-122-2/+2
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* initial VHDL supportbryan newbold2013-11-122-4/+19
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* add old TODO requests from AJbryan newbold2013-10-291-0/+25
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* need to specify .pcf file to bitgen for some casesbryan newbold2013-10-211-1/+1
| | | | This was related to an "ERROR:PhysDesignRules:2199"
* commit TODO listbryan newbold2013-10-091-0/+18
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* fix up minor xula2 typosbryan newbold2013-10-092-2/+1
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* refactor project -> exampleprojbryan newbold2013-10-094-367/+1
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* partially fix bug where synthesis continues after .ngc failurebryan newbold2013-10-091-0/+2
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* clean up main_xula2 a bitbryan newbold2013-10-091-3/+6
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* move around device-specific Makefile includes for easier target swappingbryan newbold2013-10-091-2/+5
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* spruce up sp605 build targetbryan newbold2013-10-093-30/+527
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* basic rot13 UART demo workingbryan newbold2013-10-083-0/+239
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* clean up test stuffbryan newbold2013-10-089-112/+189
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* working xula2 sim/syn/prog systembryan newbold2013-10-0811-18/+289
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* don't have outputs depend on makefilesbryan newbold2013-10-081-3/+3
| | | | | | | | If the Makefiles are tweaked, it's up to the user to 'make clean' if necessary. The way things were previously, the entire project would get rebuilt after any trivial tweak or fix.
* linting: ignore module/filename equivalencebryan newbold2013-10-061-1/+1
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* add test/ and isim/ systembryan newbold2013-10-0610-63/+214
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* fix old tb/tb.vbryan newbold2013-10-041-15/+6
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* add concept of 'board' for seperate ucfs and top level modulesbryan newbold2013-10-045-24/+34
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* add autoimpact target (pre-select bitfile)bryan newbold2013-10-041-0/+3
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* generic timingan targetbryan newbold2013-10-041-0/+3
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* backport improvements from SNG projectbryan newbold2013-10-042-3/+8
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* changed build-commits to have one argumentAndrew J Meyer2013-08-191-3/+9
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* added build commits scriptAndrew J Meyer2013-08-191-0/+31
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* typo: pre-par .ncd file for partial_timing analysisbryan newbold2013-06-271-1/+1
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* parameterize unconstrained timing analysisbryan newbold2013-06-271-2/+3
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* commit an .xco as an example of stripped project metadatabryan newbold2013-06-271-0/+76
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* a better minimalist project, including a timing constraintbryan newbold2013-06-272-31/+39
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* fix bugs with trce and parbryan newbold2013-06-271-4/+4
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* break out synth_effort as a variablebryan newbold2013-06-271-2/+3
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* fix potential problem with old etwr targetbryan newbold2013-06-271-1/+1
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* add planahead, fpga_editor, and timing targetsbryan newbold2013-06-271-13/+31
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* very minor style tweaks from downstream reposbryan newbold2013-06-193-2/+3
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* don't re-coregen after every little Makefile tweakbryan newbold2013-06-192-1/+4
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* proper Makefile syntax; device-specific; mcs bitwidthbryan newbold2013-06-193-16/+32
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* be more explicit about listing .v filesbryan newbold2013-06-061-0/+3
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* BUGSbryan newbold2013-06-051-0/+1
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* add 'make lint' verilog-build command; requires verilatorbryan newbold2013-06-051-1/+4
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* README: fix typo.Marti Bolivar2013-04-261-1/+1
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* update README, comments, .xise project filebryan newbold2013-04-263-12/+56
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