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| author | bryan newbold <bnewbold@leaflabs.com> | 2013-10-09 00:31:49 -0400 |
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| committer | bryan newbold <bnewbold@leaflabs.com> | 2013-10-09 00:31:49 -0400 |
| commit | 078932696fc9f8ec97e6efddea3019f4cb0669a9 (patch) | |
| tree | 0f8be76c5b6e5a905eafeebf69cca3d599371a2a | |
| parent | 58a4d81047891bf2bcfaa141f81b4ea34f0c3594 (diff) | |
| download | basic-hdl-template-078932696fc9f8ec97e6efddea3019f4cb0669a9.tar.gz basic-hdl-template-078932696fc9f8ec97e6efddea3019f4cb0669a9.zip | |
commit TODO list
| -rw-r--r-- | TODO.template | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/TODO.template b/TODO.template new file mode 100644 index 0000000..6b51e83 --- /dev/null +++ b/TODO.template @@ -0,0 +1,18 @@ + +switch to .EXPORT_ALL_VARIABLES and/or .ONESHELL (as a refactor/cleanup)? + or is that too gmake specific... + +BUG: synth still seems to continue even if first build (verilog compile) + fails + +add .PRECIOUS for intermediate files we don't want to get deleted + +for fpga_editor: + DISPLAY=`echo $DISPLAY |sed s/'\.0'//` fpga_editor <.ncd file> + +effort levels seem high by default: + Overall effort level (-ol): High + Router effort level (-rl): High + +impact: + impact -mode bscan -b build/sp605.bit -port auto -autoassign (needs testing) |