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* reorder contrib/xilinx.mk; re-instate ./bitfile/bryan newbold2013-11-121-16/+25
* clean up cleaning (heh)bryan newbold2013-11-121-3/+13
* fix typos revealed by going through QUICK_STARTbryan newbold2013-11-121-0/+0
* stick some basic comments into aj's build-commits.shbryan newbold2013-11-121-1/+7
* Part 3 of refactoring template files into ./contribbryan newbold2013-11-123-0/+70
* Part 1 of refactoring template files into ./contribbryan newbold2013-11-1213-85/+817
* minor cleanup of lint targetbryan newbold2013-11-121-1/+1
* initial VHDL supportbryan newbold2013-11-121-4/+16
* need to specify .pcf file to bitgen for some casesbryan newbold2013-10-211-1/+1
* partially fix bug where synthesis continues after .ngc failurebryan newbold2013-10-091-0/+2
* clean up test stuffbryan newbold2013-10-081-0/+3
* working xula2 sim/syn/prog systembryan newbold2013-10-082-2/+11
* don't have outputs depend on makefilesbryan newbold2013-10-081-3/+3
* linting: ignore module/filename equivalencebryan newbold2013-10-061-1/+1
* add test/ and isim/ systembryan newbold2013-10-061-12/+34
* add concept of 'board' for seperate ucfs and top level modulesbryan newbold2013-10-041-22/+23
* add autoimpact target (pre-select bitfile)bryan newbold2013-10-041-0/+3
* generic timingan targetbryan newbold2013-10-041-0/+3
* backport improvements from SNG projectbryan newbold2013-10-041-3/+7
* changed build-commits to have one argumentAndrew J Meyer2013-08-191-3/+9
* added build commits scriptAndrew J Meyer2013-08-191-0/+31
* typo: pre-par .ncd file for partial_timing analysisbryan newbold2013-06-271-1/+1
* parameterize unconstrained timing analysisbryan newbold2013-06-271-2/+3
* fix bugs with trce and parbryan newbold2013-06-271-4/+4
* break out synth_effort as a variablebryan newbold2013-06-271-2/+3
* fix potential problem with old etwr targetbryan newbold2013-06-271-1/+1
* add planahead, fpga_editor, and timing targetsbryan newbold2013-06-271-13/+31
* don't re-coregen after every little Makefile tweakbryan newbold2013-06-191-1/+1
* proper Makefile syntax; device-specific; mcs bitwidthbryan newbold2013-06-192-2/+10
* add 'make lint' verilog-build command; requires verilatorbryan newbold2013-06-051-1/+4
* update with bnewbold's changesbryan newbold2013-03-271-74/+63
* initial colorization stuffbryan newbold2013-03-272-1/+105
* compile in multiple tb-modules (this might slow things down for you)bryan newbold2013-03-211-2/+6
* add .ucf file referencebryan newbold2013-03-211-1/+1
* isim in the background; hackisly fix depsbryan newbold2013-03-201-4/+4
* fixes to simulatebryan newbold2013-03-201-8/+6
* fix ise project pointersbryan newbold2013-03-141-1/+1
* improvementsbryan newbold2013-03-142-12/+32
* some simulation stuffbryan newbold2013-03-131-2/+38
* move stuff around; backupbryan newbold2013-03-132-48/+17
* basic synthesis version of makefilebryan newbold2013-03-132-0/+223
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-25 04:05:08 +0000