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| author | bryan newbold <bnewbold@leaflabs.com> | 2013-10-04 21:46:17 -0400 |
|---|---|---|
| committer | bryan newbold <bnewbold@leaflabs.com> | 2013-10-04 21:46:17 -0400 |
| commit | 1ad824a33038856ae9a61379b4f78f1f6e888fe8 (patch) | |
| tree | 2bfa16bae550df4cdef9b9b360c9db3b5f159dda /contrib | |
| parent | a9cdeccc5c32979b44c3fb7cd2c86ed564adcfda (diff) | |
| download | basic-hdl-template-1ad824a33038856ae9a61379b4f78f1f6e888fe8.tar.gz basic-hdl-template-1ad824a33038856ae9a61379b4f78f1f6e888fe8.zip | |
add concept of 'board' for seperate ucfs and top level modules
Diffstat (limited to 'contrib')
| -rw-r--r-- | contrib/xilinx.mk | 45 |
1 files changed, 23 insertions, 22 deletions
diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk index 538aad1..bc67686 100644 --- a/contrib/xilinx.mk +++ b/contrib/xilinx.mk @@ -6,26 +6,27 @@ # # TODO: update these listings # -# variable description -# ---------- ------------- -# project project name (top level module should match this name) -# top_module top level module of the project -# libdir path to library directory -# libs library modules used -# vfiles all local .v files +# variable description +# ---------- ------------- +# board board target short-name +# project project name (top level module should match this name) +# top_module top level module of the project +# libdir path to library directory +# libs library modules used +# vfiles all local .v files # xilinx_cores all local .xco files -# vendor vendor of FPGA (xilinx, altera, etc.) -# family FPGA device family (spartan3e) -# part FPGA part name (xc4vfx12-10-sf363) -# flashsize size of flash for mcs file (16384) -# optfile (optional) xst extra opttions file to put in .scr -# map_opts (optional) options to give to map -# par_opts (optional) options to give to par -# intstyle (optional) intstyle option to all tools +# vendor vendor of FPGA (xilinx, altera, etc.) +# family FPGA device family (spartan3e) +# part FPGA part name (xc4vfx12-10-sf363) +# flashsize size of flash for mcs file (16384) +# optfile (optional) xst extra opttions file to put in .scr +# map_opts (optional) options to give to map +# par_opts (optional) options to give to par +# intstyle (optional) intstyle option to all tools # -# files description -# ---------- ------------ -# $(project).ucf ucf file +# files description +# ---------- ------------ +# $(board).ucf ucf file # # Library modules should have a modules.mk in their root directory, # namely $(libdir)/<libname>/module.mk, that simply adds to the vfiles @@ -145,9 +146,9 @@ build/$(project).ncd: build/$(project).ngd bash -c "$(xil_env); \ map $(intstyle) $(map_opts) $$smartguide $(project).ngd $(multithreading) $(colorize)" -build/$(project).ngd: build/$(project).ngc $(project).ucf $(project).bmm +build/$(project).ngd: build/$(project).ngc $(board).ucf $(board).bmm @bash -c "$(xil_env); \ - ngdbuild $(intstyle) $(project).ngc -bm ../$(project).bmm -sd ../cores -uc ../$(project).ucf -aul $(colorize)" + ngdbuild $(intstyle) $(project).ngc -bm ../$(board).bmm -sd ../cores -uc ../$(board).ucf -aul $(colorize)" build/$(project).ngc: $(vfiles) $(local_corengcs) build/$(project).scr build/$(project).prj @bash -c "rm build/$(project).scr; make build/$(project).scr" @@ -240,10 +241,10 @@ timingan: @bash -c "$(xil_env); timingan &" partial_timing: build/$(project)_post_map.twr - @bash -c "$(xil_env); timingan -ucf ../$(project).ucf $(project).ncd $(project).pcf $(project)_post_map.twx &" + @bash -c "$(xil_env); timingan -ucf ../$(board).ucf $(project).ncd $(project).pcf $(project)_post_map.twx &" final_timing: build/$(project)_post_par.twr - @bash -c "$(xil_env); timingan -ucf ../$(project).ucf $(project)_par.ncd $(project).pcf $(project)_post_par.twx &" + @bash -c "$(xil_env); timingan -ucf ../$(board).ucf $(project)_par.ncd $(project).pcf $(project)_post_par.twx &" lint: verilator --lint-only -Wall -I./hdl -I./cores -Wall $(top_module) |