update with bnewbold's changes

1 files changed, 63 insertions, 74 deletions

diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk
index 6fcb7d5..e6bbf8a 100644
--- a/contrib/xilinx.mk
+++ b/contrib/xilinx.mk
@@ -49,6 +49,12 @@ xil_env ?= mkdir -p build/; cd ./build; source $(iseenvfile) > /dev/null
 sim_env ?= cd ./tb; source $(iseenvfile) > /dev/null
 flashsize ?= 8192
 
+PWD := $(shell pwd)
+intstyle ?= -intstyle xflow
+colorize ?= 2>&1 | python $(PWD)/contrib/colorize.py red ERROR: yellow WARNING: green \"Number of error messages: 0\" green \"Number of error messages:\t0\" green \"Number of errors:     0\"
+
+multithreading ?= -mt 4
+
 libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs)) 
 mkfiles = Makefile $(libmks) contrib/xilinx.mk
 include $(libmks)
@@ -59,10 +65,9 @@ tbfiles ?= ./tb/tb.v
 corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc))
 local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc)))
 vfiles += $(foreach core,$(xilinx_cores),$(core:.xco=.v))
-junk += $(local_corengcs)
 tbmods = $(foreach tbm,$(tbfiles),unenclib.`basename $(tbm) .v`)
 
-.PHONY: default xilinx_cores clean twr etwr ise
+.PHONY: default xilinx_cores clean twr etwr ise isim simulate coregen impact ldimpact
 default: build/$(project).bit build/$(project).mcs
 xilinx_cores: $(corengcs)
 twr: $(project).twr
@@ -74,24 +79,24 @@ $(2): $(1)
 endef
 $(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc)))))
 
-$(coregen_work_dir)/$(project).cgp: contrib/template.cgp Makefile
-	if [ -d $(coregen_work_dir) ]; then \
+$(coregen_work_dir)/$(project).cgp: contrib/template.cgp $(mkfiles)
+	@if [ -d $(coregen_work_dir) ]; then \
 		rm -rf $(coregen_work_dir)/*; \
 	else \
 		mkdir -p $(coregen_work_dir); \
 	fi
-	cp contrib/template.cgp $@
-	echo "SET designentry = Verilog " >> $@
-	echo "SET device = $(device)" >> $@
-	echo "SET devicefamily = $(family)" >> $@
-	echo "SET package = $(device_package)" >> $@
-	echo "SET speedgrade = $(speedgrade)" >> $@
-	echo "SET workingdirectory = ./tmp/" >> $@
+	@cp contrib/template.cgp $@
+	@echo "SET designentry = Verilog " >> $@
+	@echo "SET device = $(device)" >> $@
+	@echo "SET devicefamily = $(family)" >> $@
+	@echo "SET package = $(device_package)" >> $@
+	@echo "SET speedgrade = $(speedgrade)" >> $@
+	@echo "SET workingdirectory = ./tmp/" >> $@
 
 %.ngc %.v: %.xco $(coregen_work_dir)/$(project).cgp
 	@echo "=== rebuilding $@"
-	bash -c "$(xil_env); cd ../$(coregen_work_dir); coregen -b $$OLDPWD/../$< -p $(project).cgp;"
-	xcodir=`dirname $<`; \
+	@bash -c "$(xil_env); cd ../$(coregen_work_dir); coregen -b ../$< -p $(project).cgp;"
+	@xcodir=`dirname $<`; \
 	basename=`basename $< .xco`; \
 	echo $(coregen_work_dir)/$$basename.v; \
 	if [ ! -r $(coregen_work_dir)/$$basename.ngc ]; then \
@@ -100,122 +105,106 @@ $(coregen_work_dir)/$(project).cgp: contrib/template.cgp Makefile
 	else \
 		cp $(coregen_work_dir)/$$basename.v $(coregen_work_dir)/$$basename.ngc $$xcodir; \
 	fi
-junk += $(coregen_work_dir)
 
 date = $(shell date +%F-%H-%M)
 
-# some common junk
-junk += *.xrpt
-junk += _xmsgs
-
 programming_files: build/$(project).bit build/$(project).mcs
-	mkdir -p $@/$(date)
-	mkdir -p $@/latest
-	for x in .bit .mcs .cfi _bd.bmm; do cp $(project)$$x $@/$(date)/$(project)$$x; cp $(project)$$x $@/latest/$(project)$$x; done
-	bash -c "$(xil_env); xst -help | head -1 | sed 's/^/#/' | cat - build/$(project).scr > $@/$(date)/$(project).scr"
+	@mkdir -p $@/$(date)
+	@mkdir -p $@/latest
+	@for x in .bit .mcs .cfi _bd.bmm; do cp $(project)$$x $@/$(date)/$(project)$$x; cp $(project)$$x $@/latest/$(project)$$x; done
+	@bash -c "$(xil_env); xst -help | head -1 | sed 's/^/#/' | cat - build/$(project).scr > $@/$(date)/$(project).scr"
 
 build/$(project).mcs: build/$(project).bit
-	bash -c "$(xil_env); promgen -w -s $(flashsize) -p mcs -o $(project).mcs -u 0 $(project).bit"
-junk += $(project).mcs $(project).cfi $(project).prm
+	@bash -c "$(xil_env); promgen -w -s $(flashsize) -p mcs -o $(project).mcs -u 0 $(project).bit"
 
 build/$(project).bit: build/$(project)_par.ncd
-	bash -c "$(xil_env); \
+	@bash -c "$(xil_env); \
 	bitgen $(intstyle) -g DriveDone:yes -g StartupClk:Cclk -w $(project)_par.ncd $(project).bit"
-junk += $(project).bgn $(project).bit $(project).drc $(project)_bd.bmm
 
 
 build/$(project)_par.ncd: build/$(project).ncd
-	bash -c "$(xil_env); \
-	if par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd; then \
+	@bash -c "$(xil_env); \
+	if par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd $(multithreading) $(colorize); then \
 		:; \
 	else \
-		$(MAKE) etwr; \
+		$(MAKE) etwr $(colorize); \
 	fi "
-junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad 
-junk += $(project)_par_pad.csv $(project)_par_pad.txt 
-junk += $(project)_par.grf $(project)_par.ptwx
-junk += $(project)_par.unroutes $(project)_par.xpi
 
 build/$(project).ncd: build/$(project).ngd
-	if [ -r $(project)_par.ncd ]; then \
+	@if [ -r $(project)_par.ncd ]; then \
 		cp $(project)_par.ncd smartguide.ncd; \
 		smartguide="-smartguide smartguide.ncd"; \
 	else \
 		smartguide=""; \
 	fi; \
 	bash -c "$(xil_env); \
-	map $(intstyle) $(map_opts) $$smartguide $(project).ngd "
-junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map
-junk += smartguide.ncd $(project).psr 
-junk += $(project)_summary.xml $(project)_usage.xml
+	map $(intstyle) $(map_opts) $$smartguide $(project).ngd $(multithreading) $(colorize)"
 
 build/$(project).ngd: build/$(project).ngc $(project).ucf $(project).bmm
-	bash -c "$(xil_env); \
-	ngdbuild $(intstyle) $(project).ngc -bm ../$(project).bmm -sd ../cores -uc ../$(project).ucf -aul"
-junk += $(project).ngd $(project).bld
+	@bash -c "$(xil_env); \
+	ngdbuild $(intstyle) $(project).ngc -bm ../$(project).bmm -sd ../cores -uc ../$(project).ucf -aul $(colorize)"
 
 build/$(project).ngc: $(vfiles) $(local_corengcs) build/$(project).scr build/$(project).prj
-	bash -c "$(xil_env); xst $(intstyle) -ifn $(project).scr"
-junk += xlnx_auto* build/$(top_module).lso $(project).srp 
-junk += netlist.lst xst $(project).ngc
+	@bash -c "$(xil_env); xst $(intstyle) -ifn $(project).scr $(colorize)"
 
 build/$(project).prj: $(vfiles) $(mkfiles)
-	for src in $(vfiles); do echo "verilog work ../$$src" >> $(project).tmpprj; done
-	sort -u $(project).tmpprj > $@
-	rm -f $(project).tmpprj
-junk += $(project).prj
+	@for src in $(vfiles); do echo "verilog work ../$$src" >> $(project).tmpprj; done
+	@sort -u $(project).tmpprj > $@
+	@rm -f $(project).tmpprj
 
 optfile += $(wildcard $(project).opt)
 top_module ?= $(project)
 build/$(project).scr: $(optfile) $(mkfiles) ./$(project).opt
 	mkdir -p build
-	echo "run" > $@
-	echo "-p $(part)" >> $@
-	echo "-top $(top_module)" >> $@
-	echo "-ifn $(project).prj" >> $@
-	echo "-ofn $(project).ngc" >> $@
-	cat $(optfile) >> $@
+	@echo "run" > $@
+	@echo "-p $(part)" >> $@
+	@echo "-top $(top_module)" >> $@
+	@echo "-ifn $(project).prj" >> $@
+	@echo "-ofn $(project).ngc" >> $@
+	@cat $(optfile) >> $@
 	cp $@ build/$(project).xst
-junk += $(project).scr
 
 build/$(project).post_map.twr: build/$(project).ncd
-	bash -c "$(xil_env); trce -e 10 $< $(project).pcf -o $@"
-junk += $(project).post_map.twr $(project).post_map.twx smartpreview.twr
+	@bash -c "$(xil_env); trce -e 10 $< $(project).pcf -o $@ $(colorize)"
 
 build/$(project).twr: build/$(project)_par.ncd
-	bash -c "$(xil_env); trce $< $(project).pcf -o $(project).twr"
-junk += $(project).twr $(project).twx smartpreview.twr
+	@bash -c "$(xil_env); trce $< $(project).pcf -o $(project).twr $(colorize)"
 
 build/$(project)_err.twr: build/$(project)_par.ncd
-	bash -c "$(xil_env); trce -e 10 $< $(project).pcf -o $(project)_err.twr"
-junk += $(project)_err.twr $(project)_err.twx
-
-.gitignore: $(mkfiles)
-	echo programming_files $(junk) | sed 's, ,\n,g' > .gitignore
+	@bash -c "$(xil_env); trce -e 10 $< $(project).pcf -o $(project)_err.twr $(colorize)"
 
 tb/simulate_isim.prj: $(tbfiles) $(vfiles) $(mkfiles)
-	rm -f $@
-	for f in $(vfiles); do \
+	@rm -f $@
+	@for f in $(vfiles); do \
 		echo "verilog unenclib ../$$f" >> $@; \
 	done
-	for f in $(tbfiles); do \
+	@for f in $(tbfiles); do \
 		echo "verilog unenclib ../$$f" >> $@; \
 	done
-	echo "verilog unenclib $(iseenv)/ISE/verilog/src/glbl.v" >> $@
+	@echo "verilog unenclib $(iseenv)/ISE/verilog/src/glbl.v" >> $@
 
 tb/isim: tb/simulate_isim.prj $(tbfiles) $(vfiles) $(mkfiles)
-	bash -c "$(sim_env); cd ../tb/; vlogcomp -prj simulate_isim.prj"
+	@bash -c "$(sim_env); cd ../tb/; vlogcomp -prj simulate_isim.prj $(colorize)"
 
 tb/simulate_isim: tb/isim $(tbfiles) $(vfiles) $(mkfiles)
-	bash -c "$(sim_env); cd ../tb/; fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o simulate_isim $(tbmods) unenclib.glbl"
+	@bash -c "$(sim_env); cd ../tb/; fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o simulate_isim $(tbmods) unenclib.glbl $(colorize)"
 
 simulate: tb/simulate_isim
 
 isim_cli: simulate
-	bash -c "$(sim_env); cd ../tb/; ./simulate_isim"
+	@bash -c "$(sim_env); cd ../tb/; ./simulate_isim"
 
 isim: simulate
-	bash -c "$(sim_env); cd ../tb/; ./simulate_isim -gui -view signals.wcfg &"
+	@bash -c "$(sim_env); cd ../tb/; ./simulate_isim -gui -view signals.wcfg &"
+
+coregen: $(coregen_work_dir)/$(project).cgp
+	@bash -c "$(xil_env); cd ../$(coregen_work_dir); coregen -p $(project).cgp &"
+
+impact:
+	@bash -c "$(xil_env); cd ../build; impact &"
+
+ldimpact:
+	@bash -c "$(xil_env); cd ../build; LD_PRELOAD=/usr/local/lib/libusb-driver.so impact &"
 
 ise:
 	@echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
@@ -223,9 +212,10 @@ ise:
 	@echo "!          (see README)                                    !"
 	@echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
 	@mkdir -p build
-	bash -c "$(xil_env); cd ..; ise $(project).xise &"
+	@bash -c "$(xil_env); cd ..; XIL_MAP_LOCWARN=0 ise $(project).xise &"
 
 clean: clean_synth clean_sim
+	rm -rf iseconfig
 
 clean_sim::
 	rm -f tb/simulate_isim tb/*.log tb/*.cmd tb/*.xmsgs tb/*.prj
@@ -234,5 +224,4 @@ clean_sim::
 clean_synth::
 	rm -rf build
 	rm -rf coregen-tmp
-#rm -rf $(junk)