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author | bryan newbold <bnewbold@leaflabs.com> | 2013-11-12 19:51:31 -0500 |
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committer | bryan newbold <bnewbold@leaflabs.com> | 2013-11-12 19:51:31 -0500 |
commit | f155faea835fff5b953777d97ab73ca76696fbe3 (patch) | |
tree | 1c97f7643ccc367e23f58b620a771c9d8b787305 /contrib | |
parent | ba4f457d0d84b8799a931ebb5aefbb5ed9f553c0 (diff) | |
download | basic-hdl-template-f155faea835fff5b953777d97ab73ca76696fbe3.tar.gz basic-hdl-template-f155faea835fff5b953777d97ab73ca76696fbe3.zip |
reorder contrib/xilinx.mk; re-instate ./bitfile/
Bitfiles, timing reports, and par netlists now get saved in ./bitfiles/
for every rebuild (determined by bitfile rebuild).
Diffstat (limited to 'contrib')
-rw-r--r-- | contrib/xilinx.mk | 41 |
1 files changed, 25 insertions, 16 deletions
diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk index d9b9b1f..e891c1f 100644 --- a/contrib/xilinx.mk +++ b/contrib/xilinx.mk @@ -42,6 +42,18 @@ # # NOTE: DO NOT edit this file to change settings; instead edit Makefile +# These dot-targets must come first in the file +.PHONY: default xilinx_cores clean twr_map twr_par ise isim simulate coregen \ + impact ldimpact lint planahead partial_fpga_editor final_fpga_editor \ + partial_timing final_timing tests all + +# "PRECIOUS" files will not be deleted by make as casually +.PRECIOUS: tb/%.isim + +.DEFAULT_GOAL: default +default: bitfiles +all: bitfiles + # This file only works with Xilinx stuff vendor = xilinx @@ -79,11 +91,15 @@ colorize ?= 2>&1 | python $(PWD)/contrib/colorize.py red ERROR: yellow WARNING: colorizetest ?= 2>&1 | python $(PWD)/contrib/colorize.py red FAIL green PASS # Library stuff (TODO: untested) +libs ?= +libdir ?= libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs)) mkfiles = Makefile $(libmks) contrib/xilinx.mk include $(libmks) # Setup coregen'd includes +xilinx_cores: $(corengcs) + corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc)) local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc))) verilog_files += $(foreach core,$(xilinx_cores),$(core:.xco=.v)) @@ -94,15 +110,6 @@ $(2): $(1) endef $(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc))))) -.PHONY: default xilinx_cores clean twr_map twr_par ise isim simulate coregen \ - impact ldimpact lint planahead partial_fpga_editor final_fpga_editor \ - partial_timing final_timing tests - -# "PRECIOUS" files will not be deleted by make as casually -.PRECIOUS: tb/%.isim - -default: build/$(project).bit build/$(project).mcs -xilinx_cores: $(corengcs) twr_map: build/$(project)_post_map.twr twr_par: build/$(project)_post_par.twr @@ -135,17 +142,19 @@ $(coregen_work_dir)/$(project).cgp: contrib/template.cgp cp $(coregen_work_dir)/$$basename.v $(coregen_work_dir)/$$basename.ngc $$xcodir; \ fi -date = $(shell date +%F-%H-%M) +timestamp = $(shell date +%F-%H%M) -programming_files: build/$(project).bit build/$(project).mcs - @mkdir -p $@/$(date) +bitfiles: build/$(project).bit build/$(project).mcs + @mkdir -p $@/$(timestamp) @mkdir -p $@/latest - @for x in .bit .mcs .cfi _bd.bmm; do \ - cp $(project)$$x $@/$(date)/$(project)$$x; \ - cp $(project)$$x $@/latest/$(project)$$x; \ + @# NB: _bd.bmm was listed below in the past... + @for x in .bit .mcs .cfi _par.ncd _post_par.twr _post_par.twx; do \ + cp build/$(project)$$x $@/$(timestamp)/$(project)$$x || true; \ + cp build/$(project)$$x $@/latest/$(project)$$x || true; \ done @bash -c "$(xil_env); \ - xst -help | head -1 | sed 's/^/#/' | cat - build/$(project).scr > $@/$(date)/$(project).scr" + cd ..; \ + xst -help | head -1 | sed 's/^/#/' | cat - build/$(project).scr > $@/$(timestamp)/$(project).scr" build/$(project).mcs: build/$(project).bit @bash -c "$(xil_env); \ |