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* initial VHDL supportbryan newbold2013-11-121-0/+3
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* fix up minor xula2 typosbryan newbold2013-10-091-1/+0
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* refactor project -> exampleprojbryan newbold2013-10-091-1/+1
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* move around device-specific Makefile includes for easier target swappingbryan newbold2013-10-091-2/+5
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* basic rot13 UART demo workingbryan newbold2013-10-081-0/+1
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* clean up test stuffbryan newbold2013-10-081-3/+3
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* working xula2 sim/syn/prog systembryan newbold2013-10-081-16/+17
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* add test/ and isim/ systembryan newbold2013-10-061-7/+12
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* add concept of 'board' for seperate ucfs and top level modulesbryan newbold2013-10-041-2/+10
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* very minor style tweaks from downstream reposbryan newbold2013-06-191-1/+1
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* proper Makefile syntax; device-specific; mcs bitwidthbryan newbold2013-06-191-14/+22
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* be more explicit about listing .v filesbryan newbold2013-06-061-0/+3
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* update README, comments, .xise project filebryan newbold2013-04-261-0/+4
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* update with bnewbold's changesbryan newbold2013-03-271-2/+4
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* 'main', not 'project' top module by defaultbryan newbold2013-03-141-1/+1
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* improvementsbryan newbold2013-03-141-3/+8
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* some simulation stuffbryan newbold2013-03-131-1/+4
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* move stuff around; backupbryan newbold2013-03-131-3/+5
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* basic synthesis version of makefilebryan newbold2013-03-131-0/+11