Commit message (Collapse) | Author | Age | Files | Lines | |
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* | initial VHDL support | bryan newbold | 2013-11-12 | 1 | -0/+3 |
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* | fix up minor xula2 typos | bryan newbold | 2013-10-09 | 1 | -1/+0 |
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* | refactor project -> exampleproj | bryan newbold | 2013-10-09 | 1 | -1/+1 |
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* | move around device-specific Makefile includes for easier target swapping | bryan newbold | 2013-10-09 | 1 | -2/+5 |
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* | basic rot13 UART demo working | bryan newbold | 2013-10-08 | 1 | -0/+1 |
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* | clean up test stuff | bryan newbold | 2013-10-08 | 1 | -3/+3 |
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* | working xula2 sim/syn/prog system | bryan newbold | 2013-10-08 | 1 | -16/+17 |
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* | add test/ and isim/ system | bryan newbold | 2013-10-06 | 1 | -7/+12 |
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* | add concept of 'board' for seperate ucfs and top level modules | bryan newbold | 2013-10-04 | 1 | -2/+10 |
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* | very minor style tweaks from downstream repos | bryan newbold | 2013-06-19 | 1 | -1/+1 |
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* | proper Makefile syntax; device-specific; mcs bitwidth | bryan newbold | 2013-06-19 | 1 | -14/+22 |
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* | be more explicit about listing .v files | bryan newbold | 2013-06-06 | 1 | -0/+3 |
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* | update README, comments, .xise project file | bryan newbold | 2013-04-26 | 1 | -0/+4 |
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* | update with bnewbold's changes | bryan newbold | 2013-03-27 | 1 | -2/+4 |
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* | 'main', not 'project' top module by default | bryan newbold | 2013-03-14 | 1 | -1/+1 |
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* | improvements | bryan newbold | 2013-03-14 | 1 | -3/+8 |
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* | some simulation stuff | bryan newbold | 2013-03-13 | 1 | -1/+4 |
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* | move stuff around; backup | bryan newbold | 2013-03-13 | 1 | -3/+5 |
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* | basic synthesis version of makefile | bryan newbold | 2013-03-13 | 1 | -0/+11 |