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authorbryan newbold <bnewbold@leaflabs.com>2013-06-19 13:04:46 -0400
committerbryan newbold <bnewbold@leaflabs.com>2013-06-19 13:04:46 -0400
commit10199d449f4d20786af2e8abb303d65db98f7d30 (patch)
tree462776b66d4ea656759bb27f95ccd514b6bb4464 /Makefile
parent18c3d14cad3e41d82ec231e4f519dd12449c5633 (diff)
downloadbasic-hdl-template-10199d449f4d20786af2e8abb303d65db98f7d30.tar.gz
basic-hdl-template-10199d449f4d20786af2e8abb303d65db98f7d30.zip
proper Makefile syntax; device-specific; mcs bitwidth
Diffstat (limited to 'Makefile')
-rw-r--r--Makefile36
1 files changed, 22 insertions, 14 deletions
diff --git a/Makefile b/Makefile
index d479720..16ffb50 100644
--- a/Makefile
+++ b/Makefile
@@ -1,30 +1,38 @@
# Edit project-specific variables in this file.
-project = project
-top_module = main
-vendor = xilinx
+project := project
+top_module := main
+vendor := xilinx
# This is the chipset from the Xilinx SP605 dev board
-family = spartan6
-device = xc6slx45t
-speedgrade = -3
-device_package = fgg484
-part = $(device)$(speedgrade)-$(device_package)
+family := spartan6
+device := xc6slx45t
+speedgrade := -3
+device_package := fgg484
+part := $(device)$(speedgrade)-$(device_package)
# is this build host 64 or 32 bits?
-hostbits = 64
-iseenv= /opt/Xilinx/14.3/ISE_DS/
+hostbits := 64
+iseenv := /opt/Xilinx/14.3/ISE_DS/
# list all .v files explicitly with vfiles (no hdl/*.v business)
-vfiles = hdl/project.v
+vfiles := hdl/project.v
+#vfiles += hdl/yours.v
# can only specify a single test bench file here (for now)
-tbfiles = tb/tb.v
+tbfiles := tb/tb.v
+#tbfiles += hdl/yours.v
# list of .xco files, eg "cores/bram.xco". do not include DCM files.
-#xilinx_cores = cores/bram.xco
-xilinx_cores =
+xilinx_cores :=
+#xilinx_cores += cores/example.xco
+
+# bitfile bitwidth for flash uploads
+mcs_datawidth = 16
# Bulk of the actual Makefile is in a different file.
include ./contrib/xilinx.mk
+
+# Example hardware-specific targets (eg, upload via SPI)
+include ./contrib/example-device.mk