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authorbryan newbold <bnewbold@leaflabs.com>2013-10-06 16:03:23 -0400
committerbryan newbold <bnewbold@leaflabs.com>2013-10-06 16:03:23 -0400
commita53c47f87bf6ca67fd6ce45865dc325a4216993a (patch)
tree129739243ca29671b0408afc067db5ad7411de13 /Makefile
parent7a7511363ebf3f268fd44c8f10053c9b98293b18 (diff)
downloadbasic-hdl-template-a53c47f87bf6ca67fd6ce45865dc325a4216993a.tar.gz
basic-hdl-template-a53c47f87bf6ca67fd6ce45865dc325a4216993a.zip
add test/ and isim/ system
Diffstat (limited to 'Makefile')
-rw-r--r--Makefile19
1 files changed, 12 insertions, 7 deletions
diff --git a/Makefile b/Makefile
index 8bdf2d2..eaa646e 100644
--- a/Makefile
+++ b/Makefile
@@ -24,13 +24,18 @@ part := $(device)$(speedgrade)-$(device_package)
hostbits := 64
iseenv := /opt/Xilinx/14.3/ISE_DS/
-# list all .v files explicitly with vfiles (no hdl/*.v business)
-vfiles := hdl/$(top_module)_$(board).v
-#vfiles += hdl/yours.v
-
-# can only specify a single test bench file here (for now)
-tbfiles := tb/tb.v
-#tbfiles += hdl/yours.v
+# list all .v files explicitly with verilog_files (no hdl/*.v business)
+verilog_files := hdl/$(top_module)_$(board).v
+#verilog_files += hdl/yours.v
+
+tbfiles := tb/main_tb.v
+tbfiles += tb/another_tb.v
+tbfiles += tb/trivial_test.v
+tbfiles += tb/complicated_test.v
+
+# what gets run
+alltests := test/trivial_test
+alltests += test/complicated_test
# list of .xco files, eg "cores/bram.xco". do not include DCM files.
xilinx_cores :=