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-rw-r--r--.gitignore4
-rw-r--r--Makefile19
-rw-r--r--contrib/xilinx.mk46
-rwxr-xr-xtb/another_tb.v (renamed from tb/tb.v)4
-rw-r--r--tb/another_tb.wcfg22
-rwxr-xr-xtb/complicated_test.v37
-rwxr-xr-xtb/main_tb.v36
-rw-r--r--tb/main_tb.wcfg31
-rw-r--r--tb/signals.wcfg42
-rwxr-xr-xtb/trivial_test.v36
10 files changed, 214 insertions, 63 deletions
diff --git a/.gitignore b/.gitignore
index 6d462a8..e866f68 100644
--- a/.gitignore
+++ b/.gitignore
@@ -39,6 +39,7 @@ webtalk.log
xlnx_auto_0_xdb
*.log
isim.wdb
+isim*.wdb
*.xmsgs
fuseRelaunch.cmd
isim.wdb
@@ -60,8 +61,11 @@ webtalk_pn.xml
*.prm
*.psr
*.scr
+tb/*.isim
tb/simulate_isim
tb/simulate_isim.prj
+tb/isim.compiled
+tb/test.tcl
iseconfig/
build/
coregen-tmp/
diff --git a/Makefile b/Makefile
index 8bdf2d2..eaa646e 100644
--- a/Makefile
+++ b/Makefile
@@ -24,13 +24,18 @@ part := $(device)$(speedgrade)-$(device_package)
hostbits := 64
iseenv := /opt/Xilinx/14.3/ISE_DS/
-# list all .v files explicitly with vfiles (no hdl/*.v business)
-vfiles := hdl/$(top_module)_$(board).v
-#vfiles += hdl/yours.v
-
-# can only specify a single test bench file here (for now)
-tbfiles := tb/tb.v
-#tbfiles += hdl/yours.v
+# list all .v files explicitly with verilog_files (no hdl/*.v business)
+verilog_files := hdl/$(top_module)_$(board).v
+#verilog_files += hdl/yours.v
+
+tbfiles := tb/main_tb.v
+tbfiles += tb/another_tb.v
+tbfiles += tb/trivial_test.v
+tbfiles += tb/complicated_test.v
+
+# what gets run
+alltests := test/trivial_test
+alltests += test/complicated_test
# list of .xco files, eg "cores/bram.xco". do not include DCM files.
xilinx_cores :=
diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk
index bc67686..e8ed403 100644
--- a/contrib/xilinx.mk
+++ b/contrib/xilinx.mk
@@ -13,7 +13,7 @@
# top_module top level module of the project
# libdir path to library directory
# libs library modules used
-# vfiles all local .v files
+# verilog_files all local .v files
# xilinx_cores all local .xco files
# vendor vendor of FPGA (xilinx, altera, etc.)
# family FPGA device family (spartan3e)
@@ -29,7 +29,7 @@
# $(board).ucf ucf file
#
# Library modules should have a modules.mk in their root directory,
-# namely $(libdir)/<libname>/module.mk, that simply adds to the vfiles
+# namely $(libdir)/<libname>/module.mk, that simply adds to the verilog_files
# and xilinx_cores variable.
#
# all the .xco files listed in xilinx_cores will be generated with core, with
@@ -58,6 +58,7 @@ mcs_datawidth ?= 16
PWD := $(shell pwd)
intstyle ?= -intstyle xflow
colorize ?= 2>&1 | python $(PWD)/contrib/colorize.py red ERROR: yellow WARNING: green \"Number of error messages: 0\" green \"Number of error messages:\t0\" green \"Number of errors: 0\"
+colorizetest ?= 2>&1 | python $(PWD)/contrib/colorize.py red FAIL green PASS
multithreading ?= -mt 4
@@ -67,13 +68,18 @@ include $(libmks)
# default is a single file
tbfiles ?= ./tb/tb.v
+testfiles ?=
corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc))
local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc)))
-vfiles += $(foreach core,$(xilinx_cores),$(core:.xco=.v))
+verilog_files += $(foreach core,$(xilinx_cores),$(core:.xco=.v))
+tbfiles += $(foreach tfile,$(testfiles),$(tfile))
tbmods = $(foreach tbm,$(tbfiles),unenclib.`basename $(tbm) .v`)
-.PHONY: default xilinx_cores clean twr_map twr_par ise isim simulate coregen impact ldimpact lint planahead partial_fpga_editor final_fpga_editor partial_timing final_timing
+.PHONY: default xilinx_cores clean twr_map twr_par ise isim simulate coregen impact ldimpact lint planahead partial_fpga_editor final_fpga_editor partial_timing final_timing tests
+
+.PRECIOUS: tb/%.isim
+
default: build/$(project).bit build/$(project).mcs
xilinx_cores: $(corengcs)
twr_map: build/$(project)_post_map.twr
@@ -150,12 +156,12 @@ build/$(project).ngd: build/$(project).ngc $(board).ucf $(board).bmm
@bash -c "$(xil_env); \
ngdbuild $(intstyle) $(project).ngc -bm ../$(board).bmm -sd ../cores -uc ../$(board).ucf -aul $(colorize)"
-build/$(project).ngc: $(vfiles) $(local_corengcs) build/$(project).scr build/$(project).prj
+build/$(project).ngc: $(verilog_files) $(local_corengcs) build/$(project).scr build/$(project).prj
@bash -c "rm build/$(project).scr; make build/$(project).scr"
@bash -c "$(xil_env); xst $(intstyle) -ifn $(project).scr $(colorize)"
-build/$(project).prj: $(vfiles)
- @for src in $(vfiles); do echo "verilog work ../$$src" >> $(project).tmpprj; done
+build/$(project).prj: $(verilog_files)
+ @for src in $(verilog_files); do echo "verilog work ../$$src" >> $(project).tmpprj; done
@sort -u $(project).tmpprj > $@
@rm -f $(project).tmpprj
@@ -180,9 +186,9 @@ build/$(project)_post_par.twr: build/$(project)_par.ncd
@bash -c "$(xil_env); trce $(unconst_timing) -e $(const_timing_limit) -l $(const_timing_limit) $(project)_par.ncd $(project).pcf -o $(project)_post_par.twr $(colorize)"
@echo "See $@ for timing analysis details"
-tb/simulate_isim.prj: $(tbfiles) $(vfiles) $(mkfiles)
+tb/simulate_isim.prj: $(tbfiles) $(verilog_files) $(mkfiles)
@rm -f $@
- @for f in $(vfiles); do \
+ @for f in $(verilog_files); do \
echo "verilog unenclib ../$$f" >> $@; \
done
@for f in $(tbfiles); do \
@@ -190,10 +196,11 @@ tb/simulate_isim.prj: $(tbfiles) $(vfiles) $(mkfiles)
done
@echo "verilog unenclib $(iseenv)/ISE/verilog/src/glbl.v" >> $@
-tb/isim: tb/simulate_isim.prj $(tbfiles) $(vfiles) $(mkfiles)
+tb/isim.compiled: tb/simulate_isim.prj $(tbfiles) $(verilog_files) $(mkfiles)
@bash -c "$(sim_env); cd ../tb/; vlogcomp -prj simulate_isim.prj $(colorize)"
+ @touch tb/isim.compiled
-tb/simulate_isim: tb/isim $(tbfiles) $(vfiles) $(mkfiles)
+tb/simulate_isim: tb/isim.compiled
@bash -c "$(sim_env); cd ../tb/; fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o simulate_isim $(tbmods) unenclib.glbl $(colorize)"
simulate: tb/simulate_isim
@@ -201,6 +208,21 @@ simulate: tb/simulate_isim
isim_cli: simulate
@bash -c "$(sim_env); cd ../tb/; ./simulate_isim"
+tb/%.isim: tb/%.v tb/isim.compiled
+ @uut=`basename $< .v`; \
+ bash -c "$(sim_env); cd ../tb/; fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o $$uut.isim unenclib.$$uut unenclib.glbl $(colorize)"
+
+isim/%: tb/%.isim tb/simulate_isim.prj
+ @uut=`basename $@`; \
+ bash -c "$(sim_env); cd ../tb; ./$$uut.isim -gui -view $$uut.wcfg &"
+
+test/%: tb/%.isim tb/simulate_isim.prj
+ @echo "run all" > ./tb/test.tcl
+ @uut=`basename $@`; \
+ bash -c "$(sim_env); cd ../tb/; ./$$uut.isim -tclbatch test.tcl $(colorizetest)"
+
+tests: $(alltests)
+
isim: simulate
@bash -c "$(sim_env); cd ../tb/; ./simulate_isim -gui -view signals.wcfg &"
@@ -253,7 +275,7 @@ clean: clean_synth clean_sim
rm -rf iseconfig
clean_sim::
- rm -f tb/simulate_isim tb/*.log tb/*.cmd tb/*.xmsgs tb/*.prj
+ rm -f tb/simulate_isim tb/*.log tb/*.cmd tb/*.xmsgs tb/*.prj tb/*.isim tb/isim.compiled
rm -rf tb/isim
clean_synth::
diff --git a/tb/tb.v b/tb/another_tb.v
index d5ce452..a331a0c 100755
--- a/tb/tb.v
+++ b/tb/another_tb.v
@@ -1,5 +1,5 @@
`timescale 1ps/1ps
-module tb;
+module another_tb;
reg CLK100;
always @(CLK100) begin
@@ -29,7 +29,7 @@ initial begin
#1000000 Switch_input <= 4'h01;
$display("Switch set to one");
#2000000
- $display("TEST COMPLETE");
+ $display("FAIL");
$finish();
end
diff --git a/tb/another_tb.wcfg b/tb/another_tb.wcfg
new file mode 100644
index 0000000..ad23047
--- /dev/null
+++ b/tb/another_tb.wcfg
@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
+ <db_ref_list>
+ <db_ref path="./isim.wdb" id="1" type="auto">
+ <top_modules>
+ <top_module name="another_tb" />
+ <top_module name="glbl" />
+ </top_modules>
+ </db_ref>
+ </db_ref_list>
+ <WVObjectSize size="2" />
+ <wvobject fp_name="/another_tb/LED_output" type="array" db_ref_id="1">
+ <obj_property name="ElementShortName">LED_output[3:0]</obj_property>
+ <obj_property name="ObjectShortName">LED_output[3:0]</obj_property>
+ </wvobject>
+ <wvobject fp_name="/another_tb/FPGA_RESET" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">FPGA_RESET</obj_property>
+ <obj_property name="ObjectShortName">FPGA_RESET</obj_property>
+ </wvobject>
+</wave_config>
diff --git a/tb/complicated_test.v b/tb/complicated_test.v
new file mode 100755
index 0000000..731c0c7
--- /dev/null
+++ b/tb/complicated_test.v
@@ -0,0 +1,37 @@
+`timescale 1ps/1ps
+module complicated_test;
+
+ reg CLK100;
+always @(CLK100) begin
+ #4980.00 CLK100 <= ~CLK100;
+end
+
+initial begin
+ #0 CLK100 <= 1'b0; // the first event that sets the clock in motion
+end
+
+
+reg [3:0] Switch_input;
+wire [3:0] LED_output;
+wire FPGA_RESET;
+
+main main_i (
+ .PUSH_BUTTON_RESET_RAW(FPGA_RESET),
+ .SYSTEMCLOCK(CLK100),
+ .gpio_led(LED_output),
+ .gpio_switch(Switch_input)
+ );
+
+
+initial begin
+ #0 Switch_input <= 4'h00;
+ $display("FAIL");
+ $display("Switch set to zero");
+ #1000000 Switch_input <= 4'h01;
+ $display("Switch set to one");
+ #2000000
+ $display("PASS");
+ $finish();
+end
+
+endmodule
diff --git a/tb/main_tb.v b/tb/main_tb.v
new file mode 100755
index 0000000..b0f1346
--- /dev/null
+++ b/tb/main_tb.v
@@ -0,0 +1,36 @@
+`timescale 1ps/1ps
+module main_tb;
+
+ reg CLK100;
+always @(CLK100) begin
+ #4980.00 CLK100 <= ~CLK100;
+end
+
+initial begin
+ #0 CLK100 <= 1'b0; // the first event that sets the clock in motion
+end
+
+
+reg [3:0] Switch_input;
+wire [3:0] LED_output;
+wire FPGA_RESET;
+
+main main_i (
+ .PUSH_BUTTON_RESET_RAW(FPGA_RESET),
+ .SYSTEMCLOCK(CLK100),
+ .gpio_led(LED_output),
+ .gpio_switch(Switch_input)
+ );
+
+
+initial begin
+ #0 Switch_input <= 4'h00;
+ $display("Switch set to zero");
+ #1000000 Switch_input <= 4'h01;
+ $display("Switch set to one");
+ #2000000
+ $display("PASS");
+ $finish();
+end
+
+endmodule
diff --git a/tb/main_tb.wcfg b/tb/main_tb.wcfg
new file mode 100644
index 0000000..2347506
--- /dev/null
+++ b/tb/main_tb.wcfg
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
+ <db_ref_list>
+ <db_ref path="./isim.wdb" id="1" type="auto">
+ <top_modules>
+ <top_module name="another_tb" />
+ <top_module name="glbl" />
+ <top_module name="main_tb" />
+ </top_modules>
+ </db_ref>
+ </db_ref_list>
+ <WVObjectSize size="4" />
+ <wvobject fp_name="/main_tb/CLK100" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">CLK100</obj_property>
+ <obj_property name="ObjectShortName">CLK100</obj_property>
+ </wvobject>
+ <wvobject fp_name="/main_tb/FPGA_RESET" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">FPGA_RESET</obj_property>
+ <obj_property name="ObjectShortName">FPGA_RESET</obj_property>
+ </wvobject>
+ <wvobject fp_name="/main_tb/Switch_input" type="array" db_ref_id="1">
+ <obj_property name="ElementShortName">Switch_input[3:0]</obj_property>
+ <obj_property name="ObjectShortName">Switch_input[3:0]</obj_property>
+ </wvobject>
+ <wvobject fp_name="/main_tb/LED_output" type="array" db_ref_id="1">
+ <obj_property name="ElementShortName">LED_output[3:0]</obj_property>
+ <obj_property name="ObjectShortName">LED_output[3:0]</obj_property>
+ </wvobject>
+</wave_config>
diff --git a/tb/signals.wcfg b/tb/signals.wcfg
deleted file mode 100644
index dbb5e1a..0000000
--- a/tb/signals.wcfg
+++ /dev/null
@@ -1,42 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<wave_config>
- <wave_state>
- </wave_state>
- <db_ref_list>
- <db_ref path="./isim.wdb" id="1" type="auto">
- <top_modules>
- <top_module name="glbl" />
- <top_module name="tb" />
- </top_modules>
- </db_ref>
- </db_ref_list>
- <WVObjectSize size="7" />
- <wvobject fp_name="/tb/project_i/LED_output_2" type="logic" db_ref_id="1">
- <obj_property name="ElementShortName">LED_output_2</obj_property>
- <obj_property name="ObjectShortName">LED_output_2</obj_property>
- </wvobject>
- <wvobject fp_name="/tb/project_i/Switch_input_0" type="logic" db_ref_id="1">
- <obj_property name="ElementShortName">Switch_input_0</obj_property>
- <obj_property name="ObjectShortName">Switch_input_0</obj_property>
- </wvobject>
- <wvobject fp_name="/tb/project_i/Switch_input_1" type="logic" db_ref_id="1">
- <obj_property name="ElementShortName">Switch_input_1</obj_property>
- <obj_property name="ObjectShortName">Switch_input_1</obj_property>
- </wvobject>
- <wvobject fp_name="/tb/project_i/Switch_input_2" type="logic" db_ref_id="1">
- <obj_property name="ElementShortName">Switch_input_2</obj_property>
- <obj_property name="ObjectShortName">Switch_input_2</obj_property>
- </wvobject>
- <wvobject fp_name="/tb/project_i/Switch_input_3" type="logic" db_ref_id="1">
- <obj_property name="ElementShortName">Switch_input_3</obj_property>
- <obj_property name="ObjectShortName">Switch_input_3</obj_property>
- </wvobject>
- <wvobject fp_name="/tb/project_i/SYSTEMCLOCK" type="logic" db_ref_id="1">
- <obj_property name="ElementShortName">SYSTEMCLOCK</obj_property>
- <obj_property name="ObjectShortName">SYSTEMCLOCK</obj_property>
- </wvobject>
- <wvobject fp_name="/tb/project_i/PUSH_BUTTON_RESET_RAW" type="logic" db_ref_id="1">
- <obj_property name="ElementShortName">PUSH_BUTTON_RESET_RAW</obj_property>
- <obj_property name="ObjectShortName">PUSH_BUTTON_RESET_RAW</obj_property>
- </wvobject>
-</wave_config>
diff --git a/tb/trivial_test.v b/tb/trivial_test.v
new file mode 100755
index 0000000..e12a52f
--- /dev/null
+++ b/tb/trivial_test.v
@@ -0,0 +1,36 @@
+`timescale 1ps/1ps
+module trivial_test;
+
+ reg CLK100;
+always @(CLK100) begin
+ #4980.00 CLK100 <= ~CLK100;
+end
+
+initial begin
+ #0 CLK100 <= 1'b0; // the first event that sets the clock in motion
+end
+
+
+reg [3:0] Switch_input;
+wire [3:0] LED_output;
+wire FPGA_RESET;
+
+main main_i (
+ .PUSH_BUTTON_RESET_RAW(FPGA_RESET),
+ .SYSTEMCLOCK(CLK100),
+ .gpio_led(LED_output),
+ .gpio_switch(Switch_input)
+ );
+
+
+initial begin
+ #0 Switch_input <= 4'h00;
+ $display("Switch set to zero");
+ #1000000 Switch_input <= 4'h01;
+ $display("Switch set to one");
+ #2000000
+ $display("PASS");
+ $finish();
+end
+
+endmodule
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-21 14:55:34 +0000