From a53c47f87bf6ca67fd6ce45865dc325a4216993a Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Sun, 6 Oct 2013 16:03:23 -0400
Subject: add test/ and isim/ system

---
 Makefile | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

(limited to 'Makefile')

diff --git a/Makefile b/Makefile
index 8bdf2d2..eaa646e 100644
--- a/Makefile
+++ b/Makefile
@@ -24,13 +24,18 @@ part := $(device)$(speedgrade)-$(device_package)
 hostbits := 64
 iseenv := /opt/Xilinx/14.3/ISE_DS/
 
-# list all .v files explicitly with vfiles (no hdl/*.v business)
-vfiles := hdl/$(top_module)_$(board).v
-#vfiles += hdl/yours.v
-
-# can only specify a single test bench file here (for now)
-tbfiles := tb/tb.v
-#tbfiles += hdl/yours.v
+# list all .v files explicitly with verilog_files (no hdl/*.v business)
+verilog_files := hdl/$(top_module)_$(board).v
+#verilog_files += hdl/yours.v
+
+tbfiles := tb/main_tb.v
+tbfiles += tb/another_tb.v
+tbfiles += tb/trivial_test.v
+tbfiles += tb/complicated_test.v
+
+# what gets run 
+alltests := test/trivial_test
+alltests += test/complicated_test
 
 # list of .xco files, eg "cores/bram.xco". do not include DCM files.
 xilinx_cores := 
-- 
cgit v1.2.3