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| author | bryan newbold <bnewbold@leaflabs.com> | 2013-10-08 23:48:29 -0400 |
|---|---|---|
| committer | bryan newbold <bnewbold@leaflabs.com> | 2013-10-08 23:48:29 -0400 |
| commit | 40affb5169e1d30f25a0906acb56f2cbbb74b51f (patch) | |
| tree | 55988758f3f53c3cf5dc445392a71f864510d459 /Makefile | |
| parent | 3b13cb7d690ba1891f008d2905fcfb36049c71ff (diff) | |
| download | basic-hdl-template-40affb5169e1d30f25a0906acb56f2cbbb74b51f.tar.gz basic-hdl-template-40affb5169e1d30f25a0906acb56f2cbbb74b51f.zip | |
basic rot13 UART demo working
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -27,6 +27,7 @@ iseenv := /opt/Xilinx/14.3/ISE_DS/ # list all .v files explicitly with verilog_files (no hdl/*.v business) verilog_files := hdl/$(top_module)_$(board).v verilog_files += hdl/rot13.v +verilog_files += hdl/simple_uart.v #verilog_files += hdl/yours.v tbfiles := tb/rot13_tb.v |