From 40affb5169e1d30f25a0906acb56f2cbbb74b51f Mon Sep 17 00:00:00 2001
From: bryan newbold <bnewbold@leaflabs.com>
Date: Tue, 8 Oct 2013 23:48:29 -0400
Subject: basic rot13 UART demo working

---
 Makefile | 1 +
 1 file changed, 1 insertion(+)

(limited to 'Makefile')

diff --git a/Makefile b/Makefile
index 039004f..b7bbe6b 100644
--- a/Makefile
+++ b/Makefile
@@ -27,6 +27,7 @@ iseenv := /opt/Xilinx/14.3/ISE_DS/
 # list all .v files explicitly with verilog_files (no hdl/*.v business)
 verilog_files := hdl/$(top_module)_$(board).v
 verilog_files += hdl/rot13.v
+verilog_files += hdl/simple_uart.v
 #verilog_files += hdl/yours.v
 
 tbfiles := tb/rot13_tb.v
-- 
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