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| author | Andrew J Meyer <ajm@leaflabs.com> | 2013-03-06 18:47:43 -0500 |
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| committer | Andrew J Meyer <ajm@leaflabs.com> | 2013-03-06 18:47:43 -0500 |
| commit | 0754c0f771c51d48107c5c96d79a512ce56cce0a (patch) | |
| tree | d444913b56cc430f6c4b6050af6226e669919438 /testbench/simulate_isim.prj | |
| parent | 25e9b58c4a438292e9d07151c0f2ce73d1ed64f8 (diff) | |
| download | fpga-lube-0754c0f771c51d48107c5c96d79a512ce56cce0a.tar.gz fpga-lube-0754c0f771c51d48107c5c96d79a512ce56cce0a.zip | |
added the base files
Diffstat (limited to 'testbench/simulate_isim.prj')
| -rw-r--r-- | testbench/simulate_isim.prj | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/testbench/simulate_isim.prj b/testbench/simulate_isim.prj new file mode 100644 index 0000000..e610cc5 --- /dev/null +++ b/testbench/simulate_isim.prj @@ -0,0 +1,3 @@ +verilog unenclib ../hdl/project.v
+verilog unenclib tb.v
+verilog unenclib /opt/Xilinx/14.3/ISE_DS/ISE/verilog/src/glbl.v
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