From 0754c0f771c51d48107c5c96d79a512ce56cce0a Mon Sep 17 00:00:00 2001 From: Andrew J Meyer Date: Wed, 6 Mar 2013 18:47:43 -0500 Subject: added the base files --- testbench/simulate_isim.prj | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 testbench/simulate_isim.prj (limited to 'testbench/simulate_isim.prj') diff --git a/testbench/simulate_isim.prj b/testbench/simulate_isim.prj new file mode 100644 index 0000000..e610cc5 --- /dev/null +++ b/testbench/simulate_isim.prj @@ -0,0 +1,3 @@ +verilog unenclib ../hdl/project.v +verilog unenclib tb.v +verilog unenclib /opt/Xilinx/14.3/ISE_DS/ISE/verilog/src/glbl.v -- cgit v1.2.3