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Diffstat (limited to 'TODO.template')
| -rw-r--r-- | TODO.template | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/TODO.template b/TODO.template index 89a0d5e..cc47521 100644 --- a/TODO.template +++ b/TODO.template @@ -7,6 +7,8 @@ BUG: synth still seems to continue even if first build (verilog compile) add .PRECIOUS for intermediate files we don't want to get deleted +'lint' should use vfiles, not -I./hdl + for fpga_editor: DISPLAY=`echo $DISPLAY |sed s/'\.0'//` fpga_editor <.ncd file> |