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| author | bryan newbold <bnewbold@leaflabs.com> | 2013-11-12 10:44:08 -0500 |
|---|---|---|
| committer | bryan newbold <bnewbold@leaflabs.com> | 2013-11-12 10:44:08 -0500 |
| commit | af94c066b7d5c93d98c7938954e4ef1409a71d13 (patch) | |
| tree | 0725d2607509efb41fdfe9f6c1531c4558ef4dc2 /TODO.template | |
| parent | 12fb9032819dde0ccd38dfc2645abbffb891cca9 (diff) | |
| download | basic-hdl-template-af94c066b7d5c93d98c7938954e4ef1409a71d13.tar.gz basic-hdl-template-af94c066b7d5c93d98c7938954e4ef1409a71d13.zip | |
fold BUGS into TODO.template
Diffstat (limited to 'TODO.template')
| -rw-r--r-- | TODO.template | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/TODO.template b/TODO.template index 89a0d5e..cc47521 100644 --- a/TODO.template +++ b/TODO.template @@ -7,6 +7,8 @@ BUG: synth still seems to continue even if first build (verilog compile) add .PRECIOUS for intermediate files we don't want to get deleted +'lint' should use vfiles, not -I./hdl + for fpga_editor: DISPLAY=`echo $DISPLAY |sed s/'\.0'//` fpga_editor <.ncd file> |