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-rw-r--r--BUGS2
-rw-r--r--TODO.template2
2 files changed, 2 insertions, 2 deletions
diff --git a/BUGS b/BUGS
deleted file mode 100644
index 389d42b..0000000
--- a/BUGS
+++ /dev/null
@@ -1,2 +0,0 @@
-For some reason ./tb/isim.sdb can swell to 8GB or more.
-'lint' should use vfiles, not -I./hdl
diff --git a/TODO.template b/TODO.template
index 89a0d5e..cc47521 100644
--- a/TODO.template
+++ b/TODO.template
@@ -7,6 +7,8 @@ BUG: synth still seems to continue even if first build (verilog compile)
add .PRECIOUS for intermediate files we don't want to get deleted
+'lint' should use vfiles, not -I./hdl
+
for fpga_editor:
DISPLAY=`echo $DISPLAY |sed s/'\.0'//` fpga_editor <.ncd file>