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| author | bryan newbold <bnewbold@leaflabs.com> | 2013-03-10 18:59:48 -0400 |
|---|---|---|
| committer | bryan newbold <bnewbold@leaflabs.com> | 2013-03-10 18:59:48 -0400 |
| commit | 039cc87ffdd5889083e2c834b07fe367554fc8eb (patch) | |
| tree | 672e006a3c9b2ca5af20acd096fb577238aeac5e /README | |
| parent | 0754c0f771c51d48107c5c96d79a512ce56cce0a (diff) | |
| download | basic-hdl-template-039cc87ffdd5889083e2c834b07fe367554fc8eb.tar.gz basic-hdl-template-039cc87ffdd5889083e2c834b07fe367554fc8eb.zip | |
add basic gitignore
Diffstat (limited to 'README')
| -rw-r--r-- | README | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -6,7 +6,7 @@ everything a can where things will still build. Build a bitstream (to upload to an FPGA, preconfigured as Spartan 6 chip in one of the conf files) via: -.synth_project/make.sh +./synth_project/make.sh the toplevel ucf (constraints mapping netlist objects from the verilog compilation to hardware resources, and place and routing and timing constraints) @@ -31,4 +31,4 @@ signals from your design that are saves in the wcfg. ./testbench/tb.v is the toplevel testbench file for simulation. -Please improve and push!
\ No newline at end of file +Please improve and push! |