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Diffstat (limited to 'README')
| -rw-r--r-- | README | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -6,7 +6,7 @@ everything a can where things will still build. Build a bitstream (to upload to an FPGA, preconfigured as Spartan 6 chip in one of the conf files) via: -.synth_project/make.sh +./synth_project/make.sh the toplevel ucf (constraints mapping netlist objects from the verilog compilation to hardware resources, and place and routing and timing constraints) @@ -31,4 +31,4 @@ signals from your design that are saves in the wcfg. ./testbench/tb.v is the toplevel testbench file for simulation. -Please improve and push!
\ No newline at end of file +Please improve and push! |