From 039cc87ffdd5889083e2c834b07fe367554fc8eb Mon Sep 17 00:00:00 2001 From: bryan newbold Date: Sun, 10 Mar 2013 18:59:48 -0400 Subject: add basic gitignore --- README | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'README') diff --git a/README b/README index 00e6343..9e5a5ad 100644 --- a/README +++ b/README @@ -6,7 +6,7 @@ everything a can where things will still build. Build a bitstream (to upload to an FPGA, preconfigured as Spartan 6 chip in one of the conf files) via: -.synth_project/make.sh +./synth_project/make.sh the toplevel ucf (constraints mapping netlist objects from the verilog compilation to hardware resources, and place and routing and timing constraints) @@ -31,4 +31,4 @@ signals from your design that are saves in the wcfg. ./testbench/tb.v is the toplevel testbench file for simulation. -Please improve and push! \ No newline at end of file +Please improve and push! -- cgit v1.2.3