Various fixes, working with Maple

26 files changed, 742 insertions, 139 deletions

diff --git a/libmaple/adc.h b/libmaple/adc.h
index 11aa5f6..f98a5f2 100644
--- a/libmaple/adc.h
+++ b/libmaple/adc.h
@@ -43,29 +43,32 @@ extern "C"{
  *
  * Need to up the sample time if otherwise... see datasheet */
 
-/* We'll only use ADC1 for now...  */
-#define ADC_BASE                 0x40012400
-#define ADC_SR                   *(volatile uint32*)(ADC_BASE + 0)
-#define ADC_CR1                  *(volatile uint32*)(ADC_BASE + 0x4)
-#define ADC_CR2                  *(volatile uint32*)(ADC_BASE + 0x8)
-#define ADC_SMPR1                *(volatile uint32*)(ADC_BASE + 0xC)
-#define ADC_SMPR2                *(volatile uint32*)(ADC_BASE + 0x10)
-#define ADC_SQR1                 *(volatile uint32*)(ADC_BASE + 0x2C)
-#define ADC_SQR3                 *(volatile uint32*)(ADC_BASE + 0x34)
-#define ADC_DR                   *(volatile uint32*)(ADC_BASE + 0x4C)
+/* TODO: We'll only use ADC1 for now...  */
+#define ADC1_BASE                 0x40012400
+#define ADC2_BASE                 0x40012400
+#define ADC3_BASE                 0x40012400
+
+#define ADC_SR                   *(volatile uint32*)(ADC1_BASE + 0)
+#define ADC_CR1                  *(volatile uint32*)(ADC1_BASE + 0x4)
+#define ADC_CR2                  *(volatile uint32*)(ADC1_BASE + 0x8)
+#define ADC_SMPR1                *(volatile uint32*)(ADC1_BASE + 0xC)
+#define ADC_SMPR2                *(volatile uint32*)(ADC1_BASE + 0x10)
+#define ADC_SQR1                 *(volatile uint32*)(ADC1_BASE + 0x2C)
+#define ADC_SQR3                 *(volatile uint32*)(ADC1_BASE + 0x34)
+#define ADC_DR                   *(volatile uint32*)(ADC1_BASE + 0x4C)
 
 #define CR2_EXTSEL_SWSTART       (0xE << 16)
 #define CR2_RSTCAL               (BIT(3))
 #define CR2_EXTTRIG              (BIT(20))
 
 /* Bit banded bits  */
-#define CR2_ADON_BIT             *(volatile uint32*)(BITBAND_PERI(ADC_BASE+0x8, 0))
-#define CR2_CAL_BIT              *(volatile uint32*)(BITBAND_PERI(ADC_BASE+0x8, 2))
-#define CR2_RSTCAL_BIT           *(volatile uint32*)(BITBAND_PERI(ADC_BASE+0x8, 3))
-#define CR2_SWSTART_BIT          *(volatile uint32*)(BITBAND_PERI(ADC_BASE+0x8 + 2, 6))
-#define SR_EOC_BIT               *(volatile uint32*)(BITBAND_PERI(ADC_BASE+0, 1))
+#define CR2_ADON_BIT             *(volatile uint32*)(BITBAND_PERI(ADC1_BASE+0x8, 0))
+#define CR2_CAL_BIT              *(volatile uint32*)(BITBAND_PERI(ADC1_BASE+0x8, 2))
+#define CR2_RSTCAL_BIT           *(volatile uint32*)(BITBAND_PERI(ADC1_BASE+0x8, 3))
+#define CR2_SWSTART_BIT          *(volatile uint32*)(BITBAND_PERI(ADC1_BASE+0x8 + 2, 6))
+#define SR_EOC_BIT               *(volatile uint32*)(BITBAND_PERI(ADC1_BASE+0, 1))
 
-#define NR_ANALOG_PINS           29
+// NR_ANALOG_PINS is board specific
 
 /* Initialize ADC1 to do one-shot conversions  */
 void adc_init(void);
@@ -88,8 +91,6 @@ static inline int adc_read(int channel) {
     return ADC_DR;
 }
 
-
-
 #ifdef __cplusplus
 } // extern "C"
 #endif
diff --git a/libmaple/dac.c b/libmaple/dac.c
new file mode 100644
index 0000000..ffc34f8
--- /dev/null
+++ b/libmaple/dac.c
@@ -0,0 +1,67 @@
+
+/* *****************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Bryan Newbold.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ * ****************************************************************************/
+
+#include "libmaple.h"
+#include "rcc.h"
+#include "gpio.h"
+#include "dac.h"
+
+// Only one, so global to this file
+DAC_Map *dac = (DAC_Map*)(DAC_BASE);
+
+// This numbering follows the registers (1-indexed)
+#define DAC_CHA     1
+#define DAC_CHB     2
+
+// Sets up the DAC peripheral
+void dac_init(void) {
+
+    // First turn on the clock
+    rcc_clk_enable(RCC_DAC);
+
+    // Then setup ANALOG mode on PA4 and PA5 
+    gpio_set_mode(GPIOA_BASE,  4, CNF_INPUT_ANALOG);
+    gpio_set_mode(GPIOA_BASE,  5, CNF_INPUT_ANALOG);
+
+    // Then do register stuff.
+    // Default does no triggering, and buffered output, so all good.
+    dac->CR |= DAC_CR_EN1;
+    dac->CR |= DAC_CR_EN2;
+
+}
+
+void dac_write(uint8 chan, uint16 val) {
+
+    switch(chan) {
+        case DAC_CHA:
+            dac->DHR12R1 = 0x0FFF & val;
+            break;
+        case DAC_CHB:
+            dac->DHR12R2 = 0x0FFF & val;
+            break;
+        default:    
+            ASSERT(0);  // Shouldn't get here
+    }
+}
diff --git a/libmaple/dac.h b/libmaple/dac.h
new file mode 100644
index 0000000..de1fd3f
--- /dev/null
+++ b/libmaple/dac.h
@@ -0,0 +1,108 @@
+/* *****************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Bryan Newbold.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ * ****************************************************************************/
+
+/* 
+ * See ../notes/dac.txt for more info
+ */
+
+#ifndef _DAC_H_
+#define _DAC_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#define DAC_BASE  0x40007400
+
+typedef struct {
+   volatile uint32 CR;
+   volatile uint32 SWTRIGR;
+   volatile uint32 DHR12R1;
+   volatile uint32 DHR12L1;
+   volatile uint32 DHR8R1;
+   volatile uint32 DHR12R2;
+   volatile uint32 DHR12L2;
+   volatile uint32 DHR8R2;
+   volatile uint32 DHR12RD;
+   volatile uint32 DHR12LD;
+   volatile uint32 DHR8RD;
+   volatile uint32 DOR1;
+   volatile uint32 DOR2;
+} DAC_Map;
+
+
+// And here are the register bit ranges
+#define DAC_CR_EN1      BIT(0)
+#define DAC_CR_BOFF1    BIT(1)
+#define DAC_CR_TEN1     BIT(2)
+#define DAC_CR_TSEL1    (BIT(3) | BIT(4) | BIT(5))
+#define DAC_CR_WAVE1    (BIT(6) | BIT(7))
+#define DAC_CR_MAMP1    (BIT(8) | BIT(9) | BIT(10) | BIT(11))
+#define DAC_CR_DMAEN1   BIT(12)
+#define DAC_CR_EN2      BIT(16)
+#define DAC_CR_BOFF2    BIT(17)
+#define DAC_CR_TEN2     BIT(18)
+#define DAC_CR_TSEL2    (BIT(19) | BIT(20) | BIT(21))
+#define DAC_CR_WAVE2    (BIT(22) | BIT(23))
+#define DAC_CR_MAMP2    (BIT(24) | BIT(25) | BIT(26) | BIT(27))
+#define DAC_CR_DMAEN2   BIT(28)
+
+#define DAC_SWTRIGR_SWTRIG1     BIT(0)
+#define DAC_SWTRIGR_SWTRIG2     BIT(1)
+
+#define DAC_DHR12R1_DACC1DHR     0x00000FFF
+
+#define DAC_DHR12L1_DACC1DHR     0x0000FFF0 
+
+#define DAC_DHR8R1_DACC1DHR      0x000000FF 
+
+#define DAC_DHR12R2_DACC2DHR     0x00000FFF 
+
+#define DAC_DHR12L2_DACC2DHR     0x0000FFF0
+
+#define DAC_DHR8R2_DACC2DHR      0x000000FF 
+
+#define DAC_DHR12RD_DACC1DHR     0x00000FFF
+#define DAC_DHR12RD_DACC2DHR     0x0FFF0000
+
+#define DAC_DHR12LD_DACC1DHR     0x0000FFF0 
+#define DAC_DHR12LD_DACC2DHR     0xFFF00000
+
+#define DAC_DHR8RD_DACC1DHR      0x000000FF
+#define DAC_DHR8RD_DACC2DHR      0x0000FF00
+
+#define DAC_DOR1                 0x00000FFF 
+
+#define DAC_DOR2                 0x00000FFF 
+
+
+void dac_init(void);
+void dac_write(uint8 chan, uint16 val);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+
+#endif
diff --git a/libmaple/exti.h b/libmaple/exti.h
index fdba184..2832e24 100644
--- a/libmaple/exti.h
+++ b/libmaple/exti.h
@@ -94,12 +94,11 @@
  * EXTI[5-9] -> EXT9_5
  * EXTI[10-15] -> EXT15_10
  *
- *
  * */
 
-#define NR_EXTI_CHANNELS         16
-#define NR_EXTI_PORTS             4
 #define NR_EXTI_MODES             3
+#define NR_EXTI_CHANNELS         16
+#define NR_EXTI_PORTS            NR_GPIO_PORTS       // board specific
 
 #define EXTI_IMR        0x40010400                   // Interrupt mask register
 #define EXTI_EMR        (EXTI_IMR + 0x04)            // Event mask register
@@ -139,6 +138,9 @@
 #define EXTI_CONFIG_PORTB 1
 #define EXTI_CONFIG_PORTC 2
 #define EXTI_CONFIG_PORTD 3
+#define EXTI_CONFIG_PORTE 4     // Native only
+#define EXTI_CONFIG_PORTF 5     // Native only
+#define EXTI_CONFIG_PORTG 6     // Native only
 
 
 #ifdef __cplusplus
diff --git a/libmaple/fsmc.c b/libmaple/fsmc.c
new file mode 100644
index 0000000..502b7b4
--- /dev/null
+++ b/libmaple/fsmc.c
@@ -0,0 +1,128 @@
+
+/* *****************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Bryan Newbold.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ * ****************************************************************************/
+
+#include "libmaple.h"
+#include "rcc.h"
+#include "gpio.h"
+#include "fsmc.h"
+
+// These values determined for a particular SRAM chip by following the
+// calculations in the ST FSMC application note.
+#define FSMC_ADDSET 0x0
+#define FSMC_DATAST 0x3
+
+// Sets up the FSMC peripheral to use the SRAM chip on the maple native as an
+// external segment of system memory space.
+// This implementation is for the IS62WV51216BLL 8mbit chip (55ns timing)
+void fsmc_native_sram_init(void) {
+    FSMC_Bank *bank;
+
+    // First we setup all the GPIO pins. 
+    // Data lines...
+    gpio_set_mode(GPIOD_BASE,  0, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE,  1, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE,  8, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE,  9, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE, 10, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE, 14, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE, 15, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE,  7, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE,  8, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE,  9, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE, 10, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE, 11, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE, 12, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE, 13, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE, 14, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE, 15, MODE_AF_OUTPUT_PP);
+    // Address lines...
+    gpio_set_mode(GPIOD_BASE, 11, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE, 12, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE, 13, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE,  0, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE,  1, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE,  2, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE,  3, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE,  4, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE,  5, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE, 12, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE, 13, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE, 14, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE, 15, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOG_BASE,  0, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOG_BASE,  1, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOG_BASE,  2, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOG_BASE,  3, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOG_BASE,  4, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOG_BASE,  5, MODE_AF_OUTPUT_PP);
+    // And control lines...
+    gpio_set_mode(GPIOD_BASE,  4, MODE_AF_OUTPUT_PP);   // NOE
+    gpio_set_mode(GPIOD_BASE,  5, MODE_AF_OUTPUT_PP);   // NWE
+
+    gpio_set_mode(GPIOD_BASE,  7, MODE_AF_OUTPUT_PP);   // NE1
+    gpio_set_mode(GPIOG_BASE,  9, MODE_AF_OUTPUT_PP);   // NE2
+    gpio_set_mode(GPIOG_BASE, 10, MODE_AF_OUTPUT_PP);   // NE3
+    gpio_set_mode(GPIOG_BASE, 12, MODE_AF_OUTPUT_PP);   // NE4
+
+    gpio_set_mode(GPIOE_BASE,  0, MODE_AF_OUTPUT_PP);   // NBL0
+    gpio_set_mode(GPIOE_BASE,  1, MODE_AF_OUTPUT_PP);   // NBL1
+    
+    // Next enable the clock
+    rcc_clk_enable(RCC_FSMC);
+
+    // Then we configure channel 1 the FSMC SRAM peripheral
+    // (all SRAM channels are in "Bank 1" of the FSMC)
+    bank = (FSMC_Bank*)(FSMC1_BASE);
+    
+    // Everything else is cleared (BCR1)
+    bank->BCR = 0x0000;
+
+    // Memory type is SRAM
+    bank->BCR &= ~(FSMC_BCR_MTYP);  // '00'
+
+    // Databus width is 16bits
+    bank->BCR &= ~(FSMC_BCR_MWID);  
+    bank->BCR |= 0x1 << 4;          // '01'
+
+    // Memory is nonmultiplexed
+    bank->BCR &= ~(FSMC_BCR_MUXEN); // '0'
+
+    // Need write enable to write to the chip
+    bank->BCR |= FSMC_BCR_WREN;
+
+    // Set ADDSET 
+    bank->BTR &= ~(FSMC_BTR_ADDSET);
+    bank->BTR |= (FSMC_BTR_ADDSET | FSMC_ADDSET);
+
+    // Set DATAST
+    bank->BTR &= ~(FSMC_BTR_DATAST);
+    bank->BTR |= (FSMC_BTR_DATAST | (FSMC_DATAST << 8));
+
+    // Enable channel 1
+    bank->BCR |= FSMC_BCR_MBKEN;    // '1'
+
+    // FSMC_BWTR3 not used for this simple configuration.
+}
+
diff --git a/libmaple/fsmc.h b/libmaple/fsmc.h
new file mode 100644
index 0000000..0ac4084
--- /dev/null
+++ b/libmaple/fsmc.h
@@ -0,0 +1,86 @@
+/* *****************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Bryan Newbold.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ * ****************************************************************************/
+
+/* 
+ * See ../notes/fsmc.txt for more info
+ */
+
+#ifndef _FSMC_H_
+#define _FSMC_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+// There are 4 FSMC chip-select devices; here are the SRAM-specific registers
+// for each
+
+#define FSMC1_BASE  0xA0000000
+#define FSMC2_BASE  0xA0000008
+#define FSMC3_BASE  0xA0000010
+#define FSMC4_BASE  0xA0000018
+
+typedef struct {
+   volatile uint32 BCR;
+   volatile uint32 BTR;
+   //uint32 pad[62];      // double check this?
+   //__io uint32 BWTR;
+} FSMC_Bank;
+
+// And here are the register bit ranges
+#define FSMC_BCR_MBKEN      0b00000000000000000000000000000001
+#define FSMC_BCR_MUXEN      0b00000000000000000000000000000010
+#define FSMC_BCR_MTYP       0b00000000000000000000000000001100
+#define FSMC_BCR_MWID       0b00000000000000000000000000110000
+#define FSMC_BCR_FACCEN     0b00000000000000000000000001000000
+#define FSMC_BCR_BURSTEN    0b00000000000000000000000100000000
+#define FSMC_BCR_WAITPOL    0b00000000000000000000001000000000
+#define FSMC_BCR_WRAPMOD    0b00000000000000000000010000000000
+#define FSMC_BCR_WAITCFG    0b00000000000000000000100000000000
+#define FSMC_BCR_WREN       0b00000000000000000001000000000000
+#define FSMC_BCR_WAITEN     0b00000000000000000010000000000000
+#define FSMC_BCR_EXTMOD     0b00000000000000000100000000000000
+#define FSMC_BCR_CBURSTRW   0b00000000000010000000000000000000
+#define FSMC_BTR_ADDSET     0b00000000000000000000000000001111
+#define FSMC_BTR_ADDHOLD    0b00000000000000000000000011110000
+#define FSMC_BTR_DATAST     0b00000000000000001111111100000000
+#define FSMC_BTR_BUSTURN    0b00000000000011110000000000000000
+#define FSMC_BTR_CLKDIV     0b00000000111100000000000000000000
+#define FSMC_BTR_DATALAT    0b00001111000000000000000000000000
+#define FSMC_BTR_ACCMOD     0b00110000000000000000000000000000
+#define FSMC_BWTR_ADDSET    0b00000000000000000000000000001111
+#define FSMC_BWTR_ADDHLD    0b00000000000000000000000011110000
+#define FSMC_BWTR_DATAST    0b00000000000000001111111100000000
+#define FSMC_BWTR_CLKDIV    0b00000000111100000000000000000000
+#define FSMC_BWTR_DATLAT    0b00001111000000000000000000000000
+#define FSMC_BWTR_ACCMOD    0b00110000000000000000000000000000
+
+void fsmc_native_sram_init(void);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+
+#endif
diff --git a/libmaple/gpio.c b/libmaple/gpio.c
index 3e05bd0..c5bb450 100644
--- a/libmaple/gpio.c
+++ b/libmaple/gpio.c
@@ -37,6 +37,11 @@ void gpio_init(void) {
    rcc_clk_enable(RCC_GPIOB);
    rcc_clk_enable(RCC_GPIOC);
    rcc_clk_enable(RCC_GPIOD);
+   #if NR_GPIO_PORTS >= 7
+   rcc_clk_enable(RCC_GPIOE);
+   rcc_clk_enable(RCC_GPIOF);
+   rcc_clk_enable(RCC_GPIOG);
+   #endif
    rcc_clk_enable(RCC_AFIO);
 }
 
diff --git a/libmaple/gpio.h b/libmaple/gpio.h
index 74320e6..9099c9b 100644
--- a/libmaple/gpio.h
+++ b/libmaple/gpio.h
@@ -44,10 +44,13 @@
  * - After reset, the alternate functions are not active and IO prts
  * are set to Input Floating mode */
 
-#define GPIOA_BASE               (GPIO_Port*)0x40010800
-#define GPIOB_BASE               (GPIO_Port*)0x40010C00
-#define GPIOC_BASE               (GPIO_Port*)0x40011000
-#define GPIOD_BASE               (GPIO_Port*)0x40011400
+#define GPIOA_BASE    (GPIO_Port*)0x40010800
+#define GPIOB_BASE    (GPIO_Port*)0x40010C00
+#define GPIOC_BASE    (GPIO_Port*)0x40011000
+#define GPIOD_BASE    (GPIO_Port*)0x40011400
+#define GPIOE_BASE    (GPIO_Port*)0x40011800 // High-density devices only
+#define GPIOF_BASE    (GPIO_Port*)0x40011C00 // High-density devices only
+#define GPIOG_BASE    (GPIO_Port*)0x40012000 // High-density devices only
 
 #define GPIO_SPEED_50MHZ            (0x3)
 
diff --git a/libmaple/libmaple.h b/libmaple/libmaple.h
index 5360b51..3a4042a 100644
--- a/libmaple/libmaple.h
+++ b/libmaple/libmaple.h
@@ -32,6 +32,109 @@
 #define _LIBMAPLE_H_
 
 #include "libmaple_types.h"
+
+// General configuration
+#define MAPLE_DEBUG 1
+
+// MCU-specific configuration
+#ifdef MCU_STM32F103RB  // eg, LeafLabs Maple
+
+    // Number of GPIO ports (GPIOA, GPIOB, etc), definately used
+    #define NR_GPIO_PORTS             4
+
+    // Total number of GPIO pins
+    #define NR_GPIO_PINS             39
+
+    // Number of timer devices ports, definately used
+    #define NR_TIMERS                 4
+
+    // Number of USART ports
+    #define NR_USART                  3
+
+    // Has an FSMC bus?
+    #define NR_FSMC                   0
+
+    // Has an FSMC bus?
+    #define NR_DAC_PINS               0
+
+    // USB Identifier numbers
+    // Descriptor strings must be modified by hand in usb/descriptors.c for now
+    #define VCOM_ID_VENDOR    0x1EAF
+    #define VCOM_ID_PRODUCT   0x0004
+    #define USB_DISC_BANK     GPIOC_BASE
+    #define USB_DISC_PIN      12
+    #define USB_CONFIG_MAX_POWER      (100 >> 1)
+    #define RESET_DELAY               (100)
+
+    // Where to put usercode (based on space reserved for bootloader)
+    #define USER_ADDR_ROM 0x08005000
+    #define USER_ADDR_RAM 0x20000C00
+    #define STACK_TOP     0x20000800
+
+    // Debug port settings (from ASSERT)
+    #define ERROR_LED_PORT         GPIOA_BASE
+    #define ERROR_LED_PIN          5
+    #define ERROR_USART_NUM        USART2
+    #define ERROR_USART_BAUD       9600
+    #define ERROR_TX_PIN           2
+    #define ERROR_TX_PORT          GPIOA_BASE
+
+    // Just in case, most boards have at least some memory
+    #ifndef RAMSIZE
+    #  define RAMSIZE             (caddr_t)0x50000
+    #endif
+
+    // Bitbanded Memory sections
+    #define BITBAND_SRAM_REF   0x20000000
+    #define BITBAND_SRAM_BASE  0x22000000
+    #define BITBAND_PERI_REF   0x40000000
+    #define BITBAND_PERI_BASE  0x42000000
+#endif
+
+#ifdef MCU_STM32F103ZE  
+    // eg, LeafLabs Maple Native
+    #define NR_GPIO_PORTS             7
+    #define NR_GPIO_PINS             63
+    #define NR_TIMERS                 8
+    #define NR_USART                  3
+    #define NR_FSMC                   1
+    #define NR_DAC_PINS               2
+
+    #define VCOM_ID_VENDOR    0x1EAF
+    #define VCOM_ID_PRODUCT   0x0004
+    #define USB_DISC_BANK     GPIOB_BASE
+    #define USB_DISC_PIN      8
+    #define USB_CONFIG_MAX_POWER      (100 >> 1)
+    #define RESET_DELAY               (100)
+
+    #define USER_ADDR_ROM 0x08005000
+    #define USER_ADDR_RAM 0x20000C00
+    #define STACK_TOP     0x20000800
+
+    #define ERROR_LED_PORT         GPIOC_BASE
+    #define ERROR_LED_PIN          15
+    #define ERROR_USART_NUM        USART1
+    #define ERROR_USART_BAUD       9600
+    #define ERROR_TX_PIN           10
+    #define ERROR_TX_PORT          GPIOA_BASE
+
+    #ifndef RAMSIZE
+    #  define RAMSIZE             (caddr_t)0x50000
+    #endif
+
+    #define BITBAND_SRAM_REF   0x20000000
+    #define BITBAND_SRAM_BASE  0x22000000
+    #define BITBAND_PERI_REF   0x40000000
+    #define BITBAND_PERI_BASE  0x42000000
+#endif
+
+// Make sure MCU-specific settings were defined
+#ifndef NR_GPIO_PORTS
+#error Error: No MCU type specified. Add something like -DMCU_STM32F103RB \
+       to your compiler arguments (probably in a Makefile).
+#endif
+
+// Requires board configuration info
 #include "util.h"
 
 #endif
diff --git a/libmaple/nvic.c b/libmaple/nvic.c
index 56b9940..60e7eac 100644
--- a/libmaple/nvic.c
+++ b/libmaple/nvic.c
@@ -44,8 +44,10 @@ void nvic_set_vector_table(uint32 addr, uint32 offset) {
 void nvic_irq_enable(uint32 n) {
     if (n < 32) {
         REG_SET_BIT(NVIC_ISER0, n);
-    } else {
+    } else if(n < 64) {
         REG_SET_BIT(NVIC_ISER1, n - 32);
+    } else {
+        REG_SET_BIT(NVIC_ISER2, n - 64);
     }
 }
 
@@ -56,12 +58,19 @@ void nvic_irq_enable(uint32 n) {
 void nvic_irq_disable(uint32 n) {
     if (n < 32) {
         REG_SET_BIT(NVIC_ICER0, n);
-    } else {
+    } else if(n < 64) {
         REG_SET_BIT(NVIC_ICER1, n - 32);
+    } else {
+        REG_SET_BIT(NVIC_ICER2, n - 64);
     }
 }
 
-
+void nvic_irq_disable_all(void) {
+    short n;
+    for(n=0; n<65; n++) {
+        nvic_irq_disable(n);
+    }
+}
 
 /**
  * @brief Initialice the NVIC at address addr
diff --git a/libmaple/nvic.h b/libmaple/nvic.h
index d256610..4e425c5 100644
--- a/libmaple/nvic.h
+++ b/libmaple/nvic.h
@@ -38,13 +38,13 @@
 #define NVIC_ISER0          0xE000E100
 #define NVIC_ISER1          0xE000E104
 #define NVIC_ISER2          0xE000E108
-#define NVIC_ISER3          0xE000E10C
+#define NVIC_ISER3          0xE000E10C  // Non existant?
 
 /* NVIC Interrupt Clear registers  */
 #define NVIC_ICER0          0xE000E180
 #define NVIC_ICER1          0xE000E184
 #define NVIC_ICER2          0xE000E188
-#define NVIC_ICER3          0xE000E18C
+#define NVIC_ICER3          0xE000E18C  // Non existant?
 
 /* System control registers  */
 #define SCB_VTOR            0xE000ED08  // Vector table offset register
@@ -52,10 +52,6 @@
 #define NVIC_VectTab_RAM             ((u32)0x20000000)
 #define NVIC_VectTab_FLASH           ((u32)0x08000000)
 
-/* Where to put code  */
-#define USER_ADDR_ROM 0x08005000
-#define USER_ADDR_RAM 0x20000C00
-
 #ifdef __cplusplus
 extern "C"{
 #endif
@@ -65,9 +61,14 @@ enum {
    NVIC_TIMER2  = 28,
    NVIC_TIMER3  = 29,
    NVIC_TIMER4  = 30,
+   NVIC_TIMER5  = 50,   // high density only (Maple Native)
+   NVIC_TIMER6  = 54,   // high density only (Maple Native)
+   NVIC_TIMER7  = 55,   // high density only (Maple Native)
    NVIC_USART1  = 37,
    NVIC_USART2  = 38,
    NVIC_USART3  = 39,
+   NVIC_USART4  = 52,   // high density only (Maple Native)
+   NVIC_USART5  = 53,   // high density only (Maple Native)
 };
 
 
@@ -77,6 +78,7 @@ enum {
 void nvic_init(void);
 void nvic_irq_enable(uint32 device);
 void nvic_irq_disable(uint32 device);
+void nvic_irq_disable_all(void);
 
 #ifdef __cplusplus
 }
diff --git a/libmaple/rcc.c b/libmaple/rcc.c
index ab62025..9bd2663 100644
--- a/libmaple/rcc.c
+++ b/libmaple/rcc.c
@@ -31,48 +31,6 @@
 #include "flash.h"
 #include "rcc.h"
 
-/* registers  */
-#define RCC_BASE               0x40021000
-#define RCC_CR                 (RCC_BASE + 0x0)
-#define RCC_CFGR               (RCC_BASE + 0x4)
-#define RCC_CIR                (RCC_BASE + 0x8)
-#define RCC_APB2RSTR           (RCC_BASE + 0xC)
-#define RCC_APB1RSTR           (RCC_BASE + 0x10)
-#define RCC_AHBENR             (RCC_BASE + 0x14)
-#define RCC_APB2ENR            (RCC_BASE + 0x18)
-#define RCC_APB1ENR            (RCC_BASE + 0x1C)
-#define RCC_BDCR               (RCC_BASE + 0x20)
-#define RCC_CSR                (RCC_BASE + 0x24)
-#define RCC_AHBSTR             (RCC_BASE + 0x28)
-#define RCC_CFGR2              (RCC_BASE + 0x2C)
-
-#define RCC_CFGR_USBPRE        (0x1 << 22)
-#define RCC_CFGR_ADCPRE        (0x3 << 14)
-#define RCC_CFGR_PPRE1         (0x7 << 8)
-#define RCC_CFGR_PPRE2         (0x7 << 11)
-#define RCC_CFGR_HPRE          (0xF << 4)
-#define RCC_CFGR_PLLSRC        (0x1 << 16)
-
-#define RCC_CFGR_SWS           (0x3 << 2)
-#define RCC_CFGR_SWS_PLL       (0x2 << 2)
-#define RCC_CFGR_SWS_HSE       (0x1 << 2)
-
-#define RCC_CFGR_SW            (0x3 << 0)
-#define RCC_CFGR_SW_PLL        (0x2 << 0)
-#define RCC_CFGR_SW_HSE        (0x1 << 0)
-
-/* CR status bits  */
-#define RCC_CR_HSEON           (0x1 << 16)
-#define RCC_CR_HSERDY          (0x1 << 17)
-#define RCC_CR_PLLON           (0x1 << 24)
-#define RCC_CR_PLLRDY          (0x1 << 25)
-
-#define RCC_WRITE_CFGR(val)    __write(RCC_CFGR, val)
-#define RCC_READ_CFGR()        __read(RCC_CFGR)
-
-#define RCC_WRITE_CR(val)      __write(RCC_CR, val)
-#define RCC_READ_CR()          __read(RCC_CR)
-
 enum {
    APB1,
    APB2,
@@ -90,17 +48,29 @@ static const struct rcc_dev_info rcc_dev_table[] = {
    [RCC_GPIOB]  = { .clk_domain = APB2, .line_num = 3 },
    [RCC_GPIOC]  = { .clk_domain = APB2, .line_num = 4 },
    [RCC_GPIOD]  = { .clk_domain = APB2, .line_num = 5 },
+   [RCC_GPIOE]  = { .clk_domain = APB2, .line_num = 6 }, // High-density devices only
+   [RCC_GPIOF]  = { .clk_domain = APB2, .line_num = 7 }, // High-density devices only
+   [RCC_GPIOG]  = { .clk_domain = APB2, .line_num = 8 }, // High-density devices only
    [RCC_AFIO]   = { .clk_domain = APB2, .line_num = 0 },
    [RCC_ADC1]   = { .clk_domain = APB2, .line_num = 9 },
+   [RCC_ADC2]   = { .clk_domain = APB2, .line_num = 10 },
    [RCC_USART1] = { .clk_domain = APB2, .line_num = 14 },
    [RCC_USART2] = { .clk_domain = APB1, .line_num = 17 },
    [RCC_USART3] = { .clk_domain = APB1, .line_num = 18 },
+   [RCC_USART4] = { .clk_domain = APB1, .line_num = 19 },  // High-density devices only
+   [RCC_USART5] = { .clk_domain = APB1, .line_num = 20 },  // High-density devices only
    [RCC_TIMER1] = { .clk_domain = APB2, .line_num = 11 },
    [RCC_TIMER2] = { .clk_domain = APB1, .line_num = 0 },
    [RCC_TIMER3] = { .clk_domain = APB1, .line_num = 1 },
    [RCC_TIMER4] = { .clk_domain = APB1, .line_num = 2 },
+   [RCC_TIMER5] = { .clk_domain = APB1, .line_num = 3 },   // High-density devices only
+   [RCC_TIMER6] = { .clk_domain = APB1, .line_num = 4 },   // High-density devices only
+   [RCC_TIMER7] = { .clk_domain = APB1, .line_num = 5 },   // High-density devices only
+   [RCC_TIMER8] = { .clk_domain = APB2, .line_num = 13 },  // High-density devices only
    [RCC_SPI1]   = { .clk_domain = APB2, .line_num = 12 },
    [RCC_SPI2]   = { .clk_domain = APB1, .line_num = 14 },
+   [RCC_FSMC]   = { .clk_domain = AHB,  .line_num = 8 },   // High-density devices only
+   [RCC_DAC]    = { .clk_domain = APB1, .line_num = 9 },  // High-density devices only
 };
 
 /**
diff --git a/libmaple/rcc.h b/libmaple/rcc.h
index e6a28ea..3651945 100644
--- a/libmaple/rcc.h
+++ b/libmaple/rcc.h
@@ -29,6 +29,48 @@
 #ifndef _RCC_H_
 #define _RCC_H_
 
+/* registers  */
+#define RCC_BASE               0x40021000
+#define RCC_CR                 (RCC_BASE + 0x0)
+#define RCC_CFGR               (RCC_BASE + 0x4)
+#define RCC_CIR                (RCC_BASE + 0x8)
+#define RCC_APB2RSTR           (RCC_BASE + 0xC)
+#define RCC_APB1RSTR           (RCC_BASE + 0x10)
+#define RCC_AHBENR             (RCC_BASE + 0x14)
+#define RCC_APB2ENR            (RCC_BASE + 0x18)
+#define RCC_APB1ENR            (RCC_BASE + 0x1C)
+#define RCC_BDCR               (RCC_BASE + 0x20)
+#define RCC_CSR                (RCC_BASE + 0x24)
+#define RCC_AHBSTR             (RCC_BASE + 0x28)
+#define RCC_CFGR2              (RCC_BASE + 0x2C)
+
+#define RCC_CFGR_USBPRE        (0x1 << 22)
+#define RCC_CFGR_ADCPRE        (0x3 << 14)
+#define RCC_CFGR_PPRE1         (0x7 << 8)
+#define RCC_CFGR_PPRE2         (0x7 << 11)
+#define RCC_CFGR_HPRE          (0xF << 4)
+#define RCC_CFGR_PLLSRC        (0x1 << 16)
+
+#define RCC_CFGR_SWS           (0x3 << 2)
+#define RCC_CFGR_SWS_PLL       (0x2 << 2)
+#define RCC_CFGR_SWS_HSE       (0x1 << 2)
+
+#define RCC_CFGR_SW            (0x3 << 0)
+#define RCC_CFGR_SW_PLL        (0x2 << 0)
+#define RCC_CFGR_SW_HSE        (0x1 << 0)
+
+/* CR status bits  */
+#define RCC_CR_HSEON           (0x1 << 16)
+#define RCC_CR_HSERDY          (0x1 << 17)
+#define RCC_CR_PLLON           (0x1 << 24)
+#define RCC_CR_PLLRDY          (0x1 << 25)
+
+#define RCC_WRITE_CFGR(val)    __write(RCC_CFGR, val)
+#define RCC_READ_CFGR()        __read(RCC_CFGR)
+
+#define RCC_WRITE_CR(val)      __write(RCC_CR, val)
+#define RCC_READ_CR()          __read(RCC_CR)
+
 /* sysclk source  */
 #define RCC_CLKSRC_HSI                          (0x0)
 #define RCC_CLKSRC_HSE                          (0x1)
@@ -87,34 +129,45 @@
 #define RCC_PLLMUL_15                           (0xD << 18)
 #define RCC_PLLMUL_16                           (0xE << 18)
 
-/* device numbers  */
+
+/* prescalers */
+enum {
+   RCC_PRESCALER_AHB,
+   RCC_PRESCALER_APB1,
+   RCC_PRESCALER_APB2,
+   RCC_PRESCALER_USB,
+   RCC_PRESCALER_ADC
+};
+
+// RCC Devices
 enum {
    RCC_GPIOA,
    RCC_GPIOB,
    RCC_GPIOC,
    RCC_GPIOD,
+   RCC_GPIOE,       // High-density devices only (Maple Native)
+   RCC_GPIOF,       // High-density devices only (Maple Native)
+   RCC_GPIOG,       // High-density devices only (Maple Native)
    RCC_AFIO,
    RCC_ADC1,
+   RCC_ADC2,
    RCC_USART1,
    RCC_USART2,
    RCC_USART3,
-   RCC_USART4,
-   RCC_USART5,
+   RCC_USART4,      // High-density devices only (Maple Native)
+   RCC_USART5,      // High-density devices only (Maple Native)
    RCC_TIMER1,
    RCC_TIMER2,
    RCC_TIMER3,
    RCC_TIMER4,
+   RCC_TIMER5,      // High-density devices only (Maple Native)
+   RCC_TIMER6,      // High-density devices only (Maple Native)
+   RCC_TIMER7,      // High-density devices only (Maple Native)
+   RCC_TIMER8,      // High-density devices only (Maple Native)
    RCC_SPI1,
    RCC_SPI2,
-};
-
-/* prescalers */
-enum {
-   RCC_PRESCALER_AHB,
-   RCC_PRESCALER_APB1,
-   RCC_PRESCALER_APB2,
-   RCC_PRESCALER_USB,
-   RCC_PRESCALER_ADC
+   RCC_FSMC,        // High-density devices only (Maple Native)
+   RCC_DAC,         // High-density devices only (Maple Native)
 };
 
 
@@ -125,4 +178,3 @@ void rcc_set_prescaler(uint32 prescaler, uint32 divider);
 
 #endif
 
-
diff --git a/libmaple/rules.mk b/libmaple/rules.mk
index 60673fe..8428277 100644
--- a/libmaple/rules.mk
+++ b/libmaple/rules.mk
@@ -25,6 +25,8 @@ cSRCS_$(d) := systick.c                \
               rcc.c                    \
               flash.c                  \
               spi.c                    \
+			  fsmc.c				   \
+			  dac.c					   \
               usb/usb.c                \
               usb/usb_callbacks.c      \
               usb/usb_hardware.c       \
diff --git a/libmaple/spi.h b/libmaple/spi.h
index 25c2c6b..742c1d0 100644
--- a/libmaple/spi.h
+++ b/libmaple/spi.h
@@ -36,6 +36,7 @@ extern "C" {
 /* peripheral addresses */
 #define SPI1_BASE                   0x40013000
 #define SPI2_BASE                   0x40003800
+#define SPI3_BASE                   0x40003C00
 
 /* baud rate prescaler bits */
 #define CR1_BR                      0x00000038
diff --git a/libmaple/syscalls.c b/libmaple/syscalls.c
index 63ebb1e..ec271a2 100644
--- a/libmaple/syscalls.c
+++ b/libmaple/syscalls.c
@@ -28,13 +28,6 @@
 /* _end is set in the linker command file */
 extern caddr_t _end;
 
-/* just in case, most boards have at least some memory */
-#ifndef RAMSIZE
-#  define RAMSIZE             (caddr_t)0x50000
-#endif
-
-#define STACK_TOP 0x20000800
-
 void uart_send(const char*str);
 
 /*
diff --git a/libmaple/timers.c b/libmaple/timers.c
index 6e6653c..6fa2848 100644
--- a/libmaple/timers.c
+++ b/libmaple/timers.c
@@ -28,6 +28,8 @@
  *  @brief General timer routines
  */
 
+// TODO: actually support timer5 and timer8
+
 #include "libmaple.h"
 #include "rcc.h"
 #include "nvic.h"
@@ -82,6 +84,10 @@ volatile static voidFuncPtr timer1_handlers[4];
 volatile static voidFuncPtr timer2_handlers[4];
 volatile static voidFuncPtr timer3_handlers[4];
 volatile static voidFuncPtr timer4_handlers[4];
+#if NR_TIMERS >= 8
+volatile static voidFuncPtr timer5_handlers[4]; // High-density devices only
+volatile static voidFuncPtr timer8_handlers[4]; // High-density devices only
+#endif
 
 // This function should probably be rewriten to take (timer_num, mode) and have
 // prescaler set elsewhere. The mode can be passed through to set_mode at the 
@@ -110,6 +116,20 @@ void timer_init(uint8 timer_num, uint16 prescale) {
         timer = (Timer*)TIMER4_BASE;
         rcc_clk_enable(RCC_TIMER4);
         break;
+    #if NR_TIMERS >= 8
+    case 5:
+        timer = (Timer*)TIMER5_BASE;
+        rcc_clk_enable(RCC_TIMER5);
+        break;
+    case 8:
+        timer = (Timer*)TIMER8_BASE;
+        rcc_clk_enable(RCC_TIMER8);
+        is_advanced = 1;
+        break;
+    #endif
+    default:
+        ASSERT(0);
+        return;
     }
 
     timer->CR1 = ARPE;        // No clock division
@@ -172,6 +192,9 @@ void timer_pause(uint8 timer_num) {
     case 4:
         timer = (Timer*)TIMER4_BASE;
         break;
+    default:
+        ASSERT(0);
+        return;
     }
     timer->CR1 &= ~(0x0001);    // CEN
 }
@@ -194,6 +217,9 @@ void timer_resume(uint8 timer_num) {
     case 4:
         timer = (Timer*)TIMER4_BASE;
         break;
+    default:
+        ASSERT(0);
+        return;
     }
     timer->CR1 |= 0x0001;    // CEN
 }
@@ -218,6 +244,9 @@ ASSERT(timer_num > 0 && timer_num <= 4);
     case 4:
         timer = (Timer*)TIMER4_BASE;
         break;
+    default:
+        ASSERT(0);
+        return;
     }
     timer->CNT = value;
 }
@@ -241,6 +270,9 @@ uint16 timer_get_count(uint8 timer_num) {
     case 4:
         timer = (Timer*)TIMER4_BASE;
         break;
+    default:
+        ASSERT(0);
+        return;
     }
     return timer->CNT;
 }
@@ -263,6 +295,9 @@ void timer_set_prescaler(uint8 timer_num, uint16 prescale) {
     case 4:
         timer = (Timer*)TIMER4_BASE;
         break;
+    default:
+        ASSERT(0);
+        return;
     }
     timer->PSC = prescale;
 }
@@ -286,6 +321,9 @@ void timer_set_reload(uint8 timer_num, uint16 max_reload) {
     case 4:
         timer = (Timer*)TIMER4_BASE;
         break;
+    default:
+        ASSERT(0);
+        return;
     }
     timer->ARR = max_reload;
 }
diff --git a/libmaple/timers.h b/libmaple/timers.h
index c48ef42..c49a00e 100644
--- a/libmaple/timers.h
+++ b/libmaple/timers.h
@@ -89,6 +89,10 @@ typedef volatile uint32* TimerCCR;
 #define TIMER2_BASE        0x40000000
 #define TIMER3_BASE        0x40000400
 #define TIMER4_BASE        0x40000800
+#define TIMER5_BASE        0x40000C00   // High-density devices only (Maple Native)
+#define TIMER6_BASE        0x40001000   // High-density devices only (Maple Native)
+#define TIMER7_BASE        0x40001400   // High-density devices only (Maple Native)
+#define TIMER8_BASE        0x40013400   // High-density devices only (Maple Native)
 
 #define ARPE               BIT(7)                // Auto-reload preload enable
 #define NOT_A_TIMER        0
@@ -116,6 +120,18 @@ typedef volatile uint32* TimerCCR;
 #define TIMER4_CH3_CCR     (TimerCCR)(TIMER4_BASE + 0x3C)
 #define TIMER4_CH4_CCR     (TimerCCR)(TIMER4_BASE + 0x40)
 
+// Timer5 and Timer8 are in high-density devices only (such as Maple Native).
+// Timer6 and Timer7 in these devices have no output compare pins.
+
+#define TIMER5_CH1_CCR     (TimerCCR)(TIMER5_BASE + 0x34)
+#define TIMER5_CH2_CCR     (TimerCCR)(TIMER5_BASE + 0x38)
+#define TIMER5_CH3_CCR     (TimerCCR)(TIMER5_BASE + 0x3C)
+#define TIMER5_CH4_CCR     (TimerCCR)(TIMER5_BASE + 0x40)
+
+#define TIMER8_CH1_CCR     (TimerCCR)(TIMER8_BASE + 0x34)
+#define TIMER8_CH2_CCR     (TimerCCR)(TIMER8_BASE + 0x38)
+#define TIMER8_CH3_CCR     (TimerCCR)(TIMER8_BASE + 0x3C)
+#define TIMER8_CH4_CCR     (TimerCCR)(TIMER8_BASE + 0x40)
 
 #define TIMER_DISABLED          0
 #define TIMER_PWM               1
diff --git a/libmaple/usart.c b/libmaple/usart.c
index 296a1fb..ef54ad0 100644
--- a/libmaple/usart.c
+++ b/libmaple/usart.c
@@ -33,16 +33,18 @@
 #include "nvic.h"
 #include "usart.h"
 
-#define USART1_BASE         0x40013800
-#define USART2_BASE         0x40004400
-#define USART3_BASE         0x40004800
-
-#define USART_UE            BIT(13)
-#define USART_M             BIT(12)
-#define USART_TE            BIT(3)
-#define USART_RE            BIT(2)
-#define USART_RXNEIE        BIT(5)       // read data register not empty interrupt enable
-#define USART_TC            BIT(6)
+#define USART1_BASE    0x40013800
+#define USART2_BASE    0x40004400
+#define USART3_BASE    0x40004800
+#define UART4_BASE     0x40004C00  // High-density devices only (Maple Native)
+#define UART5_BASE     0x40005000  // High-density devices only (Maple Native)
+
+#define USART_UE       BIT(13)
+#define USART_M        BIT(12)
+#define USART_TE       BIT(3)
+#define USART_RE       BIT(2)
+#define USART_RXNEIE   BIT(5)  // read data register not empty interrupt enable
+#define USART_TC       BIT(6)
 
 /* usart descriptor table  */
 struct usart_dev usart_dev_table[] = {
@@ -61,6 +63,20 @@ struct usart_dev usart_dev_table[] = {
       .rcc_dev_num = RCC_USART3,
       .nvic_dev_num = NVIC_USART3
    },
+   /*
+   #if NR_USART >= 5
+   [UART4] = {
+      .base = (usart_port*)UART4_BASE,
+      .rcc_dev_num = RCC_UART4,
+      .nvic_dev_num = NVIC_UART4
+   },
+   [UART5] = {
+      .base = (usart_port*)UART5_BASE,
+      .rcc_dev_num = RCC_UART5,
+      .nvic_dev_num = NVIC_UART5
+   },
+   #endif
+   */
 };
 
 /* usart interrupt handlers  */
@@ -75,6 +91,14 @@ void USART2_IRQHandler(void) {
 void USART3_IRQHandler(void) {
     rb_insert(&usart_dev_table[USART3].rb, (uint8)(((usart_port*)(USART3_BASE))->DR));
 }
+#if NR_USART >= 5
+void UART4_IRQHandler(void) {
+    rb_insert(&usart_dev_table[UART4].rb, (uint8)(((usart_port*)(UART4_BASE))->DR));
+}
+void UART5_IRQHandler(void) {
+    rb_insert(&usart_dev_table[UART5].rb, (uint8)(((usart_port*)(UART5_BASE))->DR));
+}
+#endif
 
 /**
  *  @brief Enable a USART in single buffer transmission mode, multibuffer
@@ -83,6 +107,7 @@ void USART3_IRQHandler(void) {
  *  @param baud Baud rate to be set at
  */
 void usart_init(uint8 usart_num, uint32 baud) {
+    ASSERT(usart_num <= NR_USART);
     usart_port *port;
     ring_buffer *ring_buf;
 
@@ -121,6 +146,18 @@ void usart_init(uint8 usart_num, uint32 baud) {
     port->CR1 |= USART_UE;
 }
 
+/**
+ *  @brief Turn off all USARTs.
+ */
+void usart_disable_all() {
+    usart_disable(USART1);
+    usart_disable(USART2);
+    usart_disable(USART3);
+    #if NR_USART >= 5
+    usart_disable(UART4);
+    usart_disable(UART5);
+    #endif
+}
 
 /**
  *  @brief Turn off a USART.
@@ -130,7 +167,7 @@ void usart_disable(uint8 usart_num) {
     usart_port *port = usart_dev_table[usart_num].base;
 
     /* TC bit must be high before disabling the usart  */
-    while ((port->SR & USART_TC) == 0)
+    while((port->CR1 & USART_UE) && !(port->SR & USART_TC))
         ;
 
     /* Disable UE */
diff --git a/libmaple/usart.h b/libmaple/usart.h
index beffa89..2bc472f 100644
--- a/libmaple/usart.h
+++ b/libmaple/usart.h
@@ -42,6 +42,8 @@ enum {
    USART1,
    USART2,
    USART3,
+   UART4,
+   UART5,
 };
 
 /* peripheral register struct  */
@@ -113,6 +115,7 @@ static inline void usart_reset_rx(uint8 usart_num) {
 
 void usart_init(uint8 usart_num, uint32 baud);
 void usart_disable(uint8 usart_num);
+void usart_disable_all();
 void usart_putstr(uint8 usart_num, const char*);
 void usart_putudec(uint8 usart_num, uint32 val);
 
diff --git a/libmaple/usb/descriptors.h b/libmaple/usb/descriptors.h
index 1efe8c1..6652942 100644
--- a/libmaple/usb/descriptors.h
+++ b/libmaple/usb/descriptors.h
@@ -16,7 +16,7 @@
 #define USB_DEVICE_SUBCLASS_CDC           0x00
 
 #define USB_CONFIG_ATTR_BUSPOWERED        0b10000000
-#define USB_CONFIG_ATTR_SELF_POWERED       0b11000000
+#define USB_CONFIG_ATTR_SELF_POWERED      0b11000000
 
 #define EP_TYPE_INTERRUPT                 0x03
 #define EP_TYPE_BULK                      0x02
diff --git a/libmaple/usb/usb.c b/libmaple/usb/usb.c
index 23cde00..026d7f0 100644
--- a/libmaple/usb/usb.c
+++ b/libmaple/usb/usb.c
@@ -118,7 +118,8 @@ void setupUSB (void) {
   pRCC->APB1ENR |= 0x00800000;
 
   /* initialize the usb application */
-  gpio_write_bit(USB_DISC_BANK,USB_DISC_PIN,0);  /* present ourselves to the host */
+  gpio_write_bit(USB_DISC_BANK, USB_DISC_PIN, 0);  /* present ourselves to the host */
+
   USB_Init();  /* low level init routine provided by st lib */
 }
 
diff --git a/libmaple/usb/usb_config.h b/libmaple/usb/usb_config.h
index 06c81ff..ba05d42 100644
--- a/libmaple/usb/usb_config.h
+++ b/libmaple/usb/usb_config.h
@@ -5,12 +5,6 @@
 
 #include "usb_lib.h"
 
-#define VCOM_ID_VENDOR    0x1EAF
-#define VCOM_ID_PRODUCT   0x0004
-
-#define USB_CONFIG_MAX_POWER      (100 >> 1)
-#define RESET_DELAY               (100)
-
 /* choose addresses to give endpoints the max 64 byte buffers */
 #define USB_BTABLE_ADDRESS        0x00
 #define VCOM_CTRL_EPNUM           0x00
@@ -46,9 +40,6 @@
 		  CNTR_ESOFM   |	   \
 		  CNTR_RESETM  )
 
-#define USB_DISC_BANK GPIOC_BASE
-#define USB_DISC_PIN  12
-
 #define F_SUSPEND_ENABLED 1
 
 #endif
diff --git a/libmaple/usb/usb_hardware.h b/libmaple/usb/usb_hardware.h
index 208fa3a..e4a26b4 100644
--- a/libmaple/usb/usb_hardware.h
+++ b/libmaple/usb/usb_hardware.h
@@ -30,7 +30,6 @@
 /* macro'd register and peripheral definitions */
 #define EXC_RETURN 0xFFFFFFF9
 #define DEFAULT_CPSR 0x61000000
-#define STACK_TOP 0x20005000
 
 #define RCC   ((u32)0x40021000)
 #define FLASH ((u32)0x40022000)
diff --git a/libmaple/util.c b/libmaple/util.c
index 36173ee..a747948 100644
--- a/libmaple/util.c
+++ b/libmaple/util.c
@@ -36,13 +36,6 @@
 #include "adc.h"
 #include "timers.h"
 
-#define ERROR_LED_PORT         GPIOA_BASE
-#define ERROR_LED_PIN          5
-#define ERROR_USART_NUM        2
-#define ERROR_USART_BAUD       9600
-#define ERROR_TX_PIN           2
-#define ERROR_TX_PORT          GPIOA_BASE
-
 /* Error assert + fade */
 void _fail(const char* file, int line, const char* exp) {
     int32  slope   = 1;
@@ -51,7 +44,7 @@ void _fail(const char* file, int line, const char* exp) {
     uint32 i       = 0;
 
     /* Turn off interrupts */
-    nvic_disable_interrupts();
+    nvic_irq_disable_all();
 
     /* Turn off timers  */
     timer_disable_all();
@@ -60,9 +53,7 @@ void _fail(const char* file, int line, const char* exp) {
     adc_disable();
 
     /* Turn off all usarts  */
-    usart_disable(1);
-    usart_disable(2);
-    usart_disable(3);
+    usart_disable_all();
 
     /* Initialize the error usart */
     gpio_set_mode(ERROR_TX_PORT, ERROR_TX_PIN, GPIO_MODE_AF_OUTPUT_PP);
@@ -76,13 +67,14 @@ void _fail(const char* file, int line, const char* exp) {
     usart_putstr(ERROR_USART_NUM, ": ");
     usart_putudec(ERROR_USART_NUM, line);
     usart_putc(ERROR_USART_NUM, '\n');
-
+    usart_putc(ERROR_USART_NUM, '\r');
+    
     /* Turn on the error LED  */
     gpio_set_mode(ERROR_LED_PORT, ERROR_LED_PIN, GPIO_MODE_OUTPUT_PP);
 
     /* Turn the USB interrupt back on so the bootloader keeps on functioning  */
-    nvic_enable_interrupt(NVIC_INT_USBHP);
-    nvic_enable_interrupt(NVIC_INT_USBLP);
+    nvic_irq_enable(NVIC_INT_USBHP);
+    nvic_irq_enable(NVIC_INT_USBLP);
 
     /* Error fade  */
     while (1) {
diff --git a/libmaple/util.h b/libmaple/util.h
index c336e21..053731a 100644
--- a/libmaple/util.h
+++ b/libmaple/util.h
@@ -32,8 +32,6 @@
 #ifndef _UTIL_H_
 #define _UTIL_H_
 
-#define MAPLE_DEBUG 0
-
 #define BIT(shift)                     (1 << (shift))
 #define BIT_MASK_SHIFT(mask, shift)    ((mask) << (shift))
 
@@ -41,11 +39,7 @@
 #define GET_BITS(x, m, n) ((((uint32)x) << (31 - (n))) >> ((31 - (n)) + (m)))
 
 /* Bit-banding macros  */
-#define BITBAND_SRAM_REF   0x20000000
-#define BITBAND_SRAM_BASE  0x22000000
 #define BITBAND_SRAM(a,b) ((BITBAND_SRAM_BASE + (a-BITBAND_SRAM_REF)*32 + (b*4)))  // Convert SRAM address
-#define BITBAND_PERI_REF   0x40000000
-#define BITBAND_PERI_BASE  0x42000000
 #define BITBAND_PERI(a,b) ((BITBAND_PERI_BASE + (a-BITBAND_PERI_REF)*32 + (b*4)))  // Convert PERI address
 
 #define REG_SET(reg, val)               (*(volatile uint32*)(reg)  = (val))