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| author | bnewbold <bnewbold@robocracy.org> | 2010-07-24 16:33:34 -0400 |
|---|---|---|
| committer | bnewbold <bnewbold@robocracy.org> | 2010-07-24 16:33:34 -0400 |
| commit | d0e353ca9f3a0986c54beab3948117bdaade700e (patch) | |
| tree | 1afedadbe21e744e62ae069a8d3fc773b68168f9 | |
| parent | 31f9eb2364bbf2ef79a3bdc64c3b692cb218db81 (diff) | |
| download | librambutan-d0e353ca9f3a0986c54beab3948117bdaade700e.tar.gz librambutan-d0e353ca9f3a0986c54beab3948117bdaade700e.zip | |
rename clock selection register
This is just a change of macro name with zero impact on the actual
binary. Looking at page 87/1003 of the STM reference manual, bits [0:1]
are the SW register which is modifiable by software, while [2:3] are SWS
and are set only by hardware.
| -rw-r--r-- | libmaple/rcc.c | 4 | ||||
| -rw-r--r-- | libmaple/rcc.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/libmaple/rcc.c b/libmaple/rcc.c index a519b67..079c4d6 100644 --- a/libmaple/rcc.c +++ b/libmaple/rcc.c @@ -99,8 +99,8 @@ static void pll_init(void) { /* select pll for system clock source */ cfgr = __read(RCC_CFGR); - cfgr &= ~RCC_CFGR_SWS; - __write(RCC_CFGR, cfgr | RCC_CFGR_SWS_PLL); + cfgr &= ~RCC_CFGR_SW; + __write(RCC_CFGR, cfgr | RCC_CFGR_SW_PLL); while (__get_bits(RCC_CFGR, 0x00000008) != 0x8) { asm volatile("nop"); diff --git a/libmaple/rcc.h b/libmaple/rcc.h index 9973bca..cb3c543 100644 --- a/libmaple/rcc.h +++ b/libmaple/rcc.h @@ -65,8 +65,8 @@ #define PLLON BIT(24) #define PLL_INPUT_CLK_HSE BIT(16) -#define RCC_CFGR_SWS 0x00000003 -#define RCC_CFGR_SWS_PLL 0x00000002 +#define RCC_CFGR_SW 0x00000003 +#define RCC_CFGR_SW_PLL 0x00000002 /* APB2 reset bits */ #define RCC_APB2RSTR_USART1RST BIT(14) |