FSMC refactor; SRAM test code

8 files changed, 684 insertions, 193 deletions

diff --git a/examples/fsmc-stress-test.cpp b/examples/fsmc-stress-test.cpp
new file mode 100644
index 0000000..12e8650
--- /dev/null
+++ b/examples/fsmc-stress-test.cpp
@@ -0,0 +1,216 @@
+/*
+
+  A low-level stress test of SRAM functionality.  Uses slow-ish timing
+  by default (DATAST = ADDSET = 0xF).
+
+  Copyright 2011 LeafLabs, LLC.
+
+  This code is released into the public domain.
+
+ */
+
+#include <stdio.h>
+#include <stddef.h>
+
+#include "wirish.h"
+#include "rcc.h"
+#include "fsmc.h"
+
+// -- SRAM config -------------------------------------------------------------
+
+// Timing configuration
+#define DATAST   0xF
+#define ADDSET   0xF
+
+// Number of SRAM chips to test
+#define N             1
+
+// How much of each to test
+#define MEM_SIZE 0x3FFF
+
+// Their start addresses in FSMC bank 1
+__io uint16 *const starts[N] = {
+    // (__io uint16 *const)FSMC_NOR_PSRAM_REGION1,
+    // (__io uint16 *const)FSMC_NOR_PSRAM_REGION2,
+    (__io uint16 *const)FSMC_NOR_PSRAM_REGION3,
+    // (__io uint16 *const)FSMC_NOR_PSRAM_REGION4,
+};
+
+// Corresponding FSMC configuration registers
+__io uint32 *const bcrs[N] = {
+    // &FSMC_NOR_PSRAM1_BASE->BCR,
+    // &FSMC_NOR_PSRAM2_BASE->BCR,
+    &FSMC_NOR_PSRAM3_BASE->BCR,
+    // &FSMC_NOR_PSRAM4_BASE->BCR,
+};
+
+// Corresponding FSMC timing registers
+__io uint32 *const btrs[N] = {
+    // &FSMC_NOR_PSRAM1_BASE->BTR,
+    // &FSMC_NOR_PSRAM2_BASE->BTR,
+    &FSMC_NOR_PSRAM3_BASE->BTR,
+    // &FSMC_NOR_PSRAM4_BASE->BTR,
+};
+
+// -- Pseudorandom number generation  -----------------------------------------
+
+const uint32 seed = 0xDEADBEEF;
+
+uint32 num_rand_calls = 0;
+
+uint32 rand(long n) {
+    num_rand_calls++;
+    return random(n);
+}
+
+// -- Printing ----------------------------------------------------------------
+
+// For snprintf()
+char snprintf_buf[200];
+
+#define ERR(fmt, ...) do {                                            \
+        snprintf(snprintf_buf, sizeof snprintf_buf,                   \
+                 "ERROR: " fmt " (seed %d, ncalls %d, line %d)",      \
+                 __VA_ARGS__, seed, num_rand_calls, __LINE__);        \
+        Serial1.println(snprintf_buf);                                \
+    } while (0)
+
+// -- setup()/loop() ----------------------------------------------------------
+
+void setup() {
+    fsmc_sram_init_gpios();
+    rcc_clk_enable(RCC_FSMC);
+
+    for (int i = 0; i < N; i++) {
+        *bcrs[i] = (FSMC_BCR_WREN |
+                    FSMC_BCR_MTYP_SRAM |
+                    FSMC_BCR_MWID_16BITS |
+                    FSMC_BCR_MBKEN);
+        *btrs[i] = (DATAST << 8) | ADDSET;
+    }
+
+    Serial1.begin(115200);
+    randomSeed(seed);
+}
+
+// stress_test() and simple_roundtrip() are the available test routines
+bool stress_test(void);
+bool simple_roundtrip(void);
+
+void loop() {
+    uint32 count = 0;
+    bool ok = true;
+    bool (*test)(void) = stress_test;
+
+    while (true) {
+        count++;
+        bool result = test();
+        ok = ok && result;
+        if (ok) {
+            snprintf(snprintf_buf, sizeof snprintf_buf,
+                     "everything ok so far, timestamp %d ms", millis());
+            Serial1.println(snprintf_buf);
+        }
+    }
+}
+
+// -- Test routines -----------------------------------------------------------
+
+bool random_trips();
+bool sequential_trips();
+
+bool stress_test(void) {
+    static int i = 0;
+    i = !i;
+
+    switch (i) {
+    case 0:
+        return random_trips();
+    default:
+        return sequential_trips();
+    }
+}
+
+bool simple_roundtrip(void) {
+    uint16 wval = 0xAB;
+
+    for (int i = 0; i < N; i++) {
+        __io uint16 *addr = starts[i] + 4;
+        snprintf(snprintf_buf, sizeof snprintf_buf, "round-trip 0x%x at %p",
+                 wval, addr);
+        Serial1.println(snprintf_buf);
+
+        *addr = wval;
+        uint16 rval = *addr;
+
+        if (rval != wval) {
+            ERR("wrote 0x%x, read 0x%x, timestamp %d", wval, rval, millis());
+            return false;
+        } else {
+            snprintf(snprintf_buf, sizeof snprintf_buf, "got back 0x%x", rval);
+            Serial1.println(snprintf_buf);
+        }
+    }
+
+    return true;
+}
+
+bool random_trips(void) {
+    for (int n = 0; n < N; n++) {
+        __io uint16 *const start = starts[n];
+
+        for (int i = 0; i < 1000; i++) {
+            uint32 offset = rand(MEM_SIZE);
+            uint32 wval = rand(0xFFFF);
+
+            *(start + offset) = wval;
+            uint32 rval = *(start + offset);
+
+            if (rval != wval) {
+                ERR("wrote 0x%x to 0x%x, read 0x%x", wval, offset, rval);
+                return false;
+            }
+        }
+    }
+    return true;
+}
+
+bool sequential_trips(void) {
+    static const uint32 seq_length = 300;
+
+    for (int n = 0; n < N; n++) {
+        __io uint16 *const start = starts[n];
+
+        for (int i = 0; i < 100; i++) {
+            uint32 start_offset = rand(MEM_SIZE - seq_length);
+
+            for (uint32 w = 0; w < seq_length; w++) {
+                uint32 offset = start_offset + w;
+
+                *(start + offset) = w;
+                uint32 r = *(start + offset);
+
+                if (w != r) {
+                    ERR("wrote 0x%x to 0x%x, read 0x%x", w, offset, r);
+                    return false;
+                }
+            }
+        }
+    }
+    return true;
+}
+
+// ----------------------------------------------------------------------------
+
+__attribute__((constructor)) void premain() {
+    init();
+}
+
+int main(void) {
+    setup();
+    while (true) {
+        loop();
+    }
+    return 0;
+}
+
diff --git a/examples/test-fsmc.cpp b/examples/test-fsmc.cpp
index 4211e4d..7db3bb7 100644
--- a/examples/test-fsmc.cpp
+++ b/examples/test-fsmc.cpp
@@ -1,113 +1,125 @@
+#include <stddef.h>             // for ptrdiff_t

+

 #include "wirish.h"

 #include "fsmc.h"

 

-#define LED_PIN BOARD_LED_PIN

-

-// System control block registers

-#define SCB_BASE    (SCB_Reg*)(0xE000ED00)

-

-// This stuff should ultimately get moved to util.h or scb.h or w/e.

-// Also in interactive test program and the HardFault IRQ handler.

-typedef struct {

-    volatile uint32 CPUID;

-    volatile uint32 ICSR;

-    volatile uint32 VTOR;

-    volatile uint32 AIRCR;

-    volatile uint32 SCR;

-    volatile uint32 CCR;

-    volatile uint32 SHPR1;

-    volatile uint32 SHPR2;

-    volatile uint32 SHPR3;

-    volatile uint32 SHCRS;

-    volatile uint32 CFSR;

-    volatile uint32 HFSR;

-    uint32 pad1;

-    volatile uint32 MMAR;

-    volatile uint32 BFAR;

-} SCB_Reg;

-

-SCB_Reg *scb;

-

-uint16 *ptr;

-int count = 0;

+#ifndef BOARD_maple_native

+#error "Sorry, this example only works on Maple Native."

+#endif

+

+// Start of FSMC SRAM bank 1

+static uint16 *const sram_start = (uint16*)0x60000000;

+// End of Maple Native SRAM chip address space (512K 16-bit words)

+static uint16 *const sram_end = (uint16*)0x60080000;

+

+void test_single_write(void);

+void test_all_addresses(void);

 

 void setup() {

-   uint32 id;

-   scb = (SCB_Reg*)SCB_BASE;

-

-   pinMode(LED_PIN, OUTPUT);

-   digitalWrite(LED_PIN,1);

-

-   Serial1.begin(9600);

-   Serial1.println("Hello World!");

-

-   Serial1.print("Init... ");

-   fsmc_native_sram_init();

-   Serial1.println("Done.");

-

-   // Start of channel1 SRAM bank (through to 0x63FFFFFF, though only a chunk

-   // of this is valid)

-   ptr = (uint16*)(0x60000000);

-

-   Serial1.print("Writing... ");

-   *ptr = 0x1234;

-   Serial1.println("Done.");

-

-   Serial1.print("Reading... ");

-   id = *ptr;

-   Serial1.print("Done: ");     // shouldn't be 0xFFFFFFFF

-   Serial1.println(id,BIN);

-

-   Serial1.println("Dumping System Control Block Registers");

-   Serial1.print("CPUID: ");

-   id = scb->CPUID;

-   Serial1.println(id,BIN);

-   Serial1.print("ICSR:  ");

-   id = scb->ICSR;

-   Serial1.println(id,BIN);

-   Serial1.print("CFSR:  ");

-   id = scb->CFSR;

-   Serial1.println(id,BIN);

-   Serial1.print("HFSR:  ");

-   id = scb->HFSR;

-   Serial1.println(id,BIN);

-   Serial1.print("MMAR:  ");

-   id = scb->MMAR;

-   Serial1.println(id,BIN);

-   Serial1.print("BFAR:  ");

-   id = scb->BFAR;

-   Serial1.println(id,BIN);

-

-   Serial1.println("Now testing all memory addresses... (will hardfault at the end)");

-   delay(3000);

+    pinMode(BOARD_LED_PIN, OUTPUT);

+    digitalWrite(BOARD_LED_PIN, HIGH);

+

+    Serial1.begin(115200);

+    Serial1.println("*** Beginning RAM chip test");

+

+    test_single_write();

+    test_all_addresses();

+

+    Serial1.println("Tests pass, finished.");

 }

 

 void loop() {

-    toggleLED();

-    delay(1);

-

-   for(int i = 0; i<100; i++) {   // modify this to speed things up

-        count++;

-        ptr++;

-        //delay(10);    // tweak this to test SRAM resiliance over time

-        *ptr = (0x0000FFFF & count);

-        if(*ptr != (0x0000FFFF & count)) {

-                Serial1.println("ERROR: mismatch, halting");

-                while(1) { }

+}

+

+void test_single_write() {

+    uint16 *ptr = sram_start;

+    uint16 tmp;

+

+    Serial1.print("Writing 0x1234... ");

+    *ptr = 0x1234;

+    Serial1.println("Done.");

+

+    Serial1.print("Reading... ");

+    tmp = *ptr;

+    Serial1.print("Done: 0x");

+    Serial1.println(tmp, HEX);

+

+    if (tmp != 0x1234) {

+        Serial1.println("Mismatch; abort.");

+        ASSERT(0);

+    }

+}

+

+void test_all_addresses() {

+    uint32 start, end;

+    uint16 count = 0;

+    uint16 *ptr;

+

+    Serial1.println("Now writing all memory addresses (unrolled loop)");

+    // Turn off the USB interrupt, as it interferes most with timing

+    // (don't turn off SysTick, or we won't get micros()).

+    SerialUSB.end();

+    start = micros();

+    for (ptr = sram_start; ptr < sram_end;) {

+        *ptr++ = count++;

+        *ptr++ = count++;

+        *ptr++ = count++;

+        *ptr++ = count++;

+        *ptr++ = count++;

+        *ptr++ = count++;

+        *ptr++ = count++;

+        *ptr++ = count++;

+        *ptr++ = count++;

+        *ptr++ = count++;

+        *ptr++ = count++;

+        *ptr++ = count++;

+        *ptr++ = count++;

+        *ptr++ = count++;

+        *ptr++ = count++;

+        *ptr++ = count++;

+    }

+    end = micros();

+    SerialUSB.begin();

+    Serial1.print("Done. Elapsed time (us): ");

+    Serial1.println(end - start);

+

+    Serial1.println("Validating writes.");

+    for (ptr = sram_start, count = 0; ptr < sram_end; ptr++, count++) {

+        uint16 value = *ptr;

+        if (value != count) {

+            Serial1.print("mismatch: 0x");

+            Serial1.print((uint32)ptr);

+            Serial1.print(" = 0x");

+            Serial1.print(value, HEX);

+            Serial1.print(", should be 0x");

+            Serial1.print(count, HEX);

+            Serial1.println(".");

+            ASSERT(0);

         }

-   }

+    }

+    Serial1.println("Done; all writes seem valid.");

+

+    ptrdiff_t nwrites = sram_end - sram_start;

+    double us_per_write = double(end-start) / double(nwrites);

+    Serial1.print("Number of writes = ");

+    Serial1.print(nwrites);

+    Serial1.print("; avg. time per write = ");

+    Serial1.print(us_per_write);

+    Serial1.print(" us (");

+    Serial1.print(1 / us_per_write);

+    Serial1.println(" MHz)");

+}

 

-   Serial1.print((uint32)(ptr),HEX);

-   Serial1.print(": ");

-   Serial1.println(*ptr,BIN);

+__attribute__((constructor)) void premain() {

+    init();

 }

 

 int main(void) {

-   init();

-   setup();

+    setup();

+

+    while (true) {

+        loop();

+    }

 

-   while (1) {

-      loop();

-   }

-   return 0;

+    return 0;

 }

diff --git a/libmaple/fsmc.c b/libmaple/fsmc.c
index 1561add..70d7e0d 100644
--- a/libmaple/fsmc.c
+++ b/libmaple/fsmc.c
@@ -33,19 +33,10 @@
 
 #ifdef STM32_HIGH_DENSITY
 
-/* These values determined for a particular SRAM chip by following the
- * calculations in the ST FSMC application note. */
-#define FSMC_ADDSET 0x0
-#define FSMC_DATAST 0x3
-
-/* Sets up the FSMC peripheral to use the SRAM chip on the maple
- * native as an external segment of system memory space.  This
- * implementation is for the IS62WV51216BLL 8mbit chip (55ns
- * timing) */
-void fsmc_native_sram_init(void) {
-    FSMC_Bank *bank;
-
-    /* First we setup all the GPIO pins. */
+/**
+ * Configure FSMC GPIOs for use with SRAM.
+ */
+void fsmc_sram_init_gpios(void) {
     /* Data lines... */
     gpio_set_mode(GPIOD,  0, GPIO_AF_OUTPUT_PP);
     gpio_set_mode(GPIOD,  1, GPIO_AF_OUTPUT_PP);
@@ -96,42 +87,6 @@ void fsmc_native_sram_init(void) {
 
     gpio_set_mode(GPIOE,  0, GPIO_AF_OUTPUT_PP);   // NBL0
     gpio_set_mode(GPIOE,  1, GPIO_AF_OUTPUT_PP);   // NBL1
-
-    /* Next enable the clock */
-    rcc_clk_enable(RCC_FSMC);
-
-    /* Then we configure channel 1 the FSMC SRAM peripheral (all SRAM
-     * channels are in "Bank 1" of the FSMC) */
-    bank = (FSMC_Bank*)(FSMC1_BASE);
-
-    /* Everything else is cleared (BCR1) */
-    bank->BCR = 0x0000;
-
-    /* Memory type is SRAM */
-    bank->BCR &= ~(FSMC_BCR_MTYP);  // '00'
-
-    /* Databus width is 16bits */
-    bank->BCR &= ~(FSMC_BCR_MWID);
-    bank->BCR |= 0x1 << 4;          // '01'
-
-    /* Memory is nonmultiplexed */
-    bank->BCR &= ~(FSMC_BCR_MUXEN); // '0'
-
-    /* Need write enable to write to the chip */
-    bank->BCR |= FSMC_BCR_WREN;
-
-    /* Set ADDSET */
-    bank->BTR &= ~(FSMC_BTR_ADDSET);
-    bank->BTR |= (FSMC_BTR_ADDSET | FSMC_ADDSET);
-
-    /* Set DATAST */
-    bank->BTR &= ~(FSMC_BTR_DATAST);
-    bank->BTR |= (FSMC_BTR_DATAST | (FSMC_DATAST << 8));
-
-    /* Enable channel 1 */
-    bank->BCR |= FSMC_BCR_MBKEN;    // '1'
-
-    /* (FSMC_BWTR3 not used for this simple configuration.) */
 }
 
 #endif  /* STM32_HIGH_DENSITY */
diff --git a/libmaple/fsmc.h b/libmaple/fsmc.h
index fed6894..fccaf0b 100644
--- a/libmaple/fsmc.h
+++ b/libmaple/fsmc.h
@@ -39,55 +39,273 @@ extern "C"{
 
 #ifdef STM32_HIGH_DENSITY
 
-// There are 4 FSMC chip-select devices; here are the SRAM-specific registers
-// for each
-
-#define FSMC1_BASE  0xA0000000
-#define FSMC2_BASE  0xA0000008
-#define FSMC3_BASE  0xA0000010
-#define FSMC4_BASE  0xA0000018
-
-typedef struct {
-    volatile uint32 BCR;
-    volatile uint32 BTR;
-    //uint32 pad[62];      // double check this?
-    //__io uint32 BWTR;
-} FSMC_Bank;
-
-// And here are the register bit ranges
-#define FSMC_BCR_MBKEN      0b00000000000000000000000000000001
-#define FSMC_BCR_MUXEN      0b00000000000000000000000000000010
-#define FSMC_BCR_MTYP       0b00000000000000000000000000001100
-#define FSMC_BCR_MWID       0b00000000000000000000000000110000
-#define FSMC_BCR_FACCEN     0b00000000000000000000000001000000
-#define FSMC_BCR_BURSTEN    0b00000000000000000000000100000000
-#define FSMC_BCR_WAITPOL    0b00000000000000000000001000000000
-#define FSMC_BCR_WRAPMOD    0b00000000000000000000010000000000
-#define FSMC_BCR_WAITCFG    0b00000000000000000000100000000000
-#define FSMC_BCR_WREN       0b00000000000000000001000000000000
-#define FSMC_BCR_WAITEN     0b00000000000000000010000000000000
-#define FSMC_BCR_EXTMOD     0b00000000000000000100000000000000
-#define FSMC_BCR_CBURSTRW   0b00000000000010000000000000000000
-#define FSMC_BTR_ADDSET     0b00000000000000000000000000001111
-#define FSMC_BTR_ADDHOLD    0b00000000000000000000000011110000
-#define FSMC_BTR_DATAST     0b00000000000000001111111100000000
-#define FSMC_BTR_BUSTURN    0b00000000000011110000000000000000
-#define FSMC_BTR_CLKDIV     0b00000000111100000000000000000000
-#define FSMC_BTR_DATALAT    0b00001111000000000000000000000000
-#define FSMC_BTR_ACCMOD     0b00110000000000000000000000000000
-#define FSMC_BWTR_ADDSET    0b00000000000000000000000000001111
-#define FSMC_BWTR_ADDHLD    0b00000000000000000000000011110000
-#define FSMC_BWTR_DATAST    0b00000000000000001111111100000000
-#define FSMC_BWTR_CLKDIV    0b00000000111100000000000000000000
-#define FSMC_BWTR_DATLAT    0b00001111000000000000000000000000
-#define FSMC_BWTR_ACCMOD    0b00110000000000000000000000000000
-
-void fsmc_native_sram_init(void);
+/*
+ * Register maps and devices
+ */
+
+/** FSMC register map type */
+typedef struct fsmc_reg_map {
+    __io uint32 BCR1; /**< SRAM/NOR-Flash chip-select control register 1 */
+    __io uint32 BTR1; /**< SRAM/NOR-Flash chip-select timing register 1 */
+    __io uint32 BCR2; /**< SRAM/NOR-Flash chip-select control register 2 */
+    __io uint32 BTR2; /**< SRAM/NOR-Flash chip-select timing register 2 */
+    __io uint32 BCR3; /**< SRAM/NOR-Flash chip-select control register 3 */
+    __io uint32 BTR3; /**< SRAM/NOR-Flash chip-select timing register 3 */
+    __io uint32 BCR4; /**< SRAM/NOR-Flash chip-select control register 4 */
+    __io uint32 BTR4; /**< SRAM/NOR-Flash chip-select timing register 4 */
+    const uint8 RESERVED1[64];  /**< Reserved */
+    __io uint32 PCR2;  /**< PC Card/NAND Flash control register 2 */
+    __io uint32 SR2;   /**< FIFO status and interrupt register 2 */
+    __io uint32 PMEM2; /**< Common memory space timing register 2 */
+    __io uint32 PATT2; /**< Attribute memory space timing register 2 */
+    const uint8 RESERVED2[4];   /**< Reserved */
+    __io uint32 ECCR2; /**< ECC result register 2 */
+    const uint8 RESERVED3[2];
+    __io uint32 PCR3;  /**< PC Card/NAND Flash control register 3 */
+    __io uint32 SR3;   /**< FIFO status and interrupt register 3 */
+    __io uint32 PMEM3; /**< Common memory space timing register 3 */
+    __io uint32 PATT3; /**< Attribute memory space timing register 3 */
+    const uint32 RESERVED4;     /**< Reserved */
+    __io uint32 ECCR3; /**< ECC result register 3 */
+    const uint8 RESERVED5[8];   /**< Reserved */
+    __io uint32 PCR4;  /**< PC Card/NAND Flash control register 4 */
+    __io uint32 SR4;   /**< FIFO status and interrupt register 4 */
+    __io uint32 PMEM4; /**< Common memory space timing register 4 */
+    __io uint32 PATT4; /**< Attribute memory space timing register 4 */
+    __io uint32 PIO4;  /**< I/O space timing register 4 */
+    const uint8 RESERVED6[80];  /**< Reserved */
+    __io uint32 BWTR1; /**< SRAM/NOR-Flash write timing register 1 */
+    const uint32 RESERVED7;     /**< Reserved */
+    __io uint32 BWTR2; /**< SRAM/NOR-Flash write timing register 2 */
+    const uint32 RESERVED8;     /**< Reserved */
+    __io uint32 BWTR3; /**< SRAM/NOR-Flash write timing register 3 */
+    const uint32 RESERVED9;     /**< Reserved */
+    __io uint32 BWTR4; /**< SRAM/NOR-Flash write timing register 4 */
+} __attribute__((packed)) fsmc_reg_map;
+
+#define __FSMC_B                        0xA0000000
+
+/** FSMC register map base pointer */
+#define FSMC_BASE                       ((struct fsmc_reg_map*)__FSMC_B)
+
+/** FSMC NOR/PSRAM register map type */
+typedef struct fsmc_nor_psram_reg_map {
+    __io uint32 BCR;            /**< Chip-select control register */
+    __io uint32 BTR;            /**< Chip-select timing register */
+    const uint8 RESERVED[252];  /**< Reserved */
+    __io uint32 BWTR;           /**< Write timing register */
+} fsmc_nor_psram_reg_map;
+
+/** FSMC NOR/PSRAM base pointer 1 */
+#define FSMC_NOR_PSRAM1_BASE ((struct fsmc_nor_psram_reg_map*)__FSMC_B)
+
+/** FSMC NOR/PSRAM base pointer 2 */
+#define FSMC_NOR_PSRAM2_BASE ((struct fsmc_nor_psram_reg_map*)(__FSMC_B + 0x8))
+
+/** FSMC NOR/PSRAM base pointer 3 */
+#define FSMC_NOR_PSRAM3_BASE ((struct fsmc_nor_psram_reg_map*)(__FSMC_B+0x10))
+
+/** FSMC NOR/PSRAM base pointer 4 */
+#define FSMC_NOR_PSRAM4_BASE ((struct fsmc_nor_psram_reg_map*)(__FSMC_B+0x18))
+
+/*
+ * Register bit definitions
+ */
+
+/* NOR/PSRAM chip-select control registers */
+
+#define FSMC_BCR_CBURSTRW_BIT           19
+#define FSMC_BCR_ASYNCWAIT_BIT          15
+#define FSMC_BCR_EXTMOD_BIT             14
+#define FSMC_BCR_WAITEN_BIT             13
+#define FSMC_BCR_WREN_BIT               12
+#define FSMC_BCR_WAITCFG_BIT            11
+#define FSMC_BCR_WRAPMOD_BIT            10
+#define FSMC_BCR_WAITPOL_BIT            9
+#define FSMC_BCR_BURSTEN_BIT            8
+#define FSMC_BCR_FACCEN_BIT             6
+#define FSMC_BCR_MUXEN_BIT              1
+#define FSMC_BCR_MBKEN_BIT              0
+
+#define FSMC_BCR_CBURSTRW               BIT(FSMC_BCR_CBURSTRW_BIT)
+#define FSMC_BCR_ASYNCWAIT              BIT(FSMC_BCR_ASYNCWAIT_BIT)
+#define FSMC_BCR_EXTMOD                 BIT(FSMC_BCR_EXTMOD_BIT)
+#define FSMC_BCR_WAITEN                 BIT(FSMC_BCR_WAITEN_BIT)
+#define FSMC_BCR_WREN                   BIT(FSMC_BCR_WREN_BIT)
+#define FSMC_BCR_WAITCFG                BIT(FSMC_BCR_WAITCFG_BIT)
+#define FSMC_BCR_WRAPMOD                BIT(FSMC_BCR_WRAPMOD_BIT)
+#define FSMC_BCR_WAITPOL                BIT(FSMC_BCR_WAITPOL_BIT)
+#define FSMC_BCR_BURSTEN                BIT(FSMC_BCR_BURSTEN_BIT)
+#define FSMC_BCR_FACCEN                 BIT(FSMC_BCR_FACCEN_BIT)
+#define FSMC_BCR_MWID                   (0x3 << 4)
+#define FSMC_BCR_MWID_8BITS             (0x0 << 4)
+#define FSMC_BCR_MWID_16BITS            (0x1 << 4)
+#define FSMC_BCR_MTYP                   (0x3 << 2)
+#define FSMC_BCR_MTYP_SRAM              (0x0 << 2)
+#define FSMC_BCR_MTYP_PSRAM             (0x1 << 2)
+#define FSMC_BCR_MTYP_NOR_FLASH         (0x2 << 2)
+#define FSMC_BCR_MUXEN                  BIT(FSMC_BCR_MUXEN_BIT)
+#define FSMC_BCR_MBKEN                  BIT(FSMC_BCR_MBKEN_BIT)
+
+/* SRAM/NOR-Flash chip-select timing registers */
+
+#define FSMC_BTR_ACCMOD                 (0x3 << 28)
+#define FSMC_BTR_ACCMOD_A               (0x0 << 28)
+#define FSMC_BTR_ACCMOD_B               (0x1 << 28)
+#define FSMC_BTR_ACCMOD_C               (0x2 << 28)
+#define FSMC_BTR_ACCMOD_D               (0x3 << 28)
+#define FSMC_BTR_DATLAT                 (0xF << 24)
+#define FSMC_BTR_CLKDIV                 (0xF << 20)
+#define FSMC_BTR_BUSTURN                (0xF << 16)
+#define FSMC_BTR_DATAST                 (0xFF << 8)
+#define FSMC_BTR_ADDHLD                 (0xF << 4)
+#define FSMC_BTR_ADDSET                 0xF
+
+/* SRAM/NOR-Flash write timing registers */
+
+#define FSMC_BWTR_ACCMOD                 (0x3 << 28)
+#define FSMC_BWTR_ACCMOD_A               (0x0 << 28)
+#define FSMC_BWTR_ACCMOD_B               (0x1 << 28)
+#define FSMC_BWTR_ACCMOD_C               (0x2 << 28)
+#define FSMC_BWTR_ACCMOD_D               (0x3 << 28)
+#define FSMC_BWTR_DATLAT                 (0xF << 24)
+#define FSMC_BWTR_CLKDIV                 (0xF << 20)
+#define FSMC_BWTR_DATAST                 (0xFF << 8)
+#define FSMC_BWTR_ADDHLD                 (0xF << 4)
+#define FSMC_BWTR_ADDSET                 0xF
+
+/* NAND Flash/PC Card controller registers */
+
+#define FSMC_PCR_ECCEN_BIT               6
+#define FSMC_PCR_PTYP_BIT                3
+#define FSMC_PCR_PBKEN_BIT               2
+#define FSMC_PCR_PWAITEN_BIT             1
+
+#define FSMC_PCR_ECCPS                   (0x7 << 17)
+#define FSMC_PCR_ECCPS_256B              (0x0 << 17)
+#define FSMC_PCR_ECCPS_512B              (0x1 << 17)
+#define FSMC_PCR_ECCPS_1024B             (0x2 << 17)
+#define FSMC_PCR_ECCPS_2048B             (0x3 << 17)
+#define FSMC_PCR_ECCPS_4096B             (0x4 << 17)
+#define FSMC_PCR_ECCPS_8192B             (0x5 << 17)
+#define FSMC_PCR_TAR                     (0xF << 13)
+#define FSMC_PCR_TCLR                    (0xF << 9)
+#define FSMC_PCR_ECCEN                   BIT(FSMC_PCR_ECCEN_BIT)
+#define FSMC_PCR_PWID                    (0x3 << 4)
+#define FSMC_PCR_PWID_8BITS              (0x0 << 4)
+#define FSMC_PCR_PWID_16BITS             (0x1 << 4)
+#define FSMC_PCR_PTYP                    BIT(FSMC_PCR_PTYP_BIT)
+#define FSMC_PCR_PTYP_PC_CF_PCMCIA       (0x0 << FSMC_PCR_PTYP_BIT)
+#define FSMC_PCR_PTYP_NAND               (0x1 << FSMC_PCR_PTYP_BIT)
+#define FSMC_PCR_PBKEN                   BIT(FSMC_PCR_PBKEN_BIT)
+#define FSMC_PCR_PWAITEN                 BIT(FSMC_PCR_PWAITEN_BIT)
+
+/* FIFO status and interrupt registers */
+
+#define FSMC_SR_FEMPT_BIT                6
+#define FSMC_SR_IFEN_BIT                 5
+#define FSMC_SR_ILEN_BIT                 4
+#define FSMC_SR_IREN_BIT                 3
+#define FSMC_SR_IFS_BIT                  2
+#define FSMC_SR_ILS_BIT                  1
+#define FSMC_SR_IRS_BIT                  0
+
+#define FSMC_SR_FEMPT                    BIT(FSMC_SR_FEMPT_BIT)
+#define FSMC_SR_IFEN                     BIT(FSMC_SR_IFEN_BIT)
+#define FSMC_SR_ILEN                     BIT(FSMC_SR_ILEN_BIT)
+#define FSMC_SR_IREN                     BIT(FSMC_SR_IREN_BIT)
+#define FSMC_SR_IFS                      BIT(FSMC_SR_IFS_BIT)
+#define FSMC_SR_ILS                      BIT(FSMC_SR_ILS_BIT)
+#define FSMC_SR_IRS                      BIT(FSMC_SR_IRS_BIT)
+
+/* Common memory space timing registers */
+
+#define FSMC_PMEM_MEMHIZ                 (0xFF << 24)
+#define FSMC_PMEM_MEMHOLD                (0xFF << 16)
+#define FSMC_PMEM_MEMWAIT                (0xFF << 8)
+#define FSMC_PMEM_MEMSET                 0xFF
+
+/* Attribute memory space timing registers */
+
+#define FSMC_PATT_ATTHIZ                 (0xFF << 24)
+#define FSMC_PATT_ATTHOLD                (0xFF << 16)
+#define FSMC_PATT_ATTWAIT                (0xFF << 8)
+#define FSMC_PATT_ATTSET                 0xFF
+
+/* I/O space timing register 4 */
+
+#define FSMC_PIO_IOHIZ                  (0xFF << 24)
+#define FSMC_PIO_IOHOLD                 (0xFF << 16)
+#define FSMC_PIO_IOWAIT                 (0xFF << 8)
+#define FSMC_PIO_IOSET                  0xFF
+
+/*
+ * Memory bank boundary addresses
+ */
+
+/** Pointer to base address of FSMC memory bank 1 (split into 4
+ * regions, each supporting 1 NOR Flash, SRAM, or PSRAM chip)  */
+#define FSMC_BANK1                      ((void*)0x60000000)
+
+/** Pointer to base address of FSMC memory bank 1, region 1 (for NOR/PSRAM) */
+#define FSMC_NOR_PSRAM_REGION1          FSMC_BANK1
+
+/** Pointer to base address of FSMC memory bank 1, region 2 (for NOR/PSRAM) */
+#define FSMC_NOR_PSRAM_REGION2          ((void*)0x64000000)
+
+/** Pointer to base address of FSMC memory bank 1, region 3 (for NOR/PSRAM) */
+#define FSMC_NOR_PSRAM_REGION3          ((void*)0x68000000)
+
+/** Pointer to base address of FSMC memory bank 1, region 4 (for NOR/PSRAM) */
+#define FSMC_NOR_PSRAM_REGION4          ((void*)0x6C000000)
+
+/** Pointer to base address of FSMC memory bank 2 (for NAND Flash) */
+#define FSMC_BANK2                      ((void*)0x70000000)
+
+/** Pointer to base address of FSMC memory bank 3 (for NAND Flash) */
+#define FSMC_BANK3                      ((void*)0x80000000)
+
+/** Pointer to base address of FSMC memory bank 4 (for PC card devices */
+#define FSMC_BANK4                      ((void*)0x90000000)
+
+/*
+ * SRAM/NOR Flash routines
+ */
+
+void fsmc_sram_init_gpios(void);
+
+/**
+ * Set the DATAST bits in the given NOR/PSRAM register map's
+ * chip-select timing register (FSMC_BTR).
+ *
+ * @param regs   NOR Flash/PSRAM register map whose chip-select timing
+ *               register to set.
+ * @param datast Value to use for DATAST bits.
+ */
+static inline void fsmc_nor_psram_set_datast(fsmc_nor_psram_reg_map *regs,
+                                             uint8 datast) {
+    regs->BTR &= ~FSMC_BTR_DATAST;
+    regs->BTR |= datast << 8;
+}
+
+/**
+ * Set the ADDHLD bits in the given NOR/PSRAM register map's chip
+ * select timing register (FSMC_BTRx).
+ *
+ * @param regs   NOR Flash/PSRAM register map whose chip-select timing
+ *               register to set.
+ * @param addset Value to use for ADDSET bits.
+ */
+static inline void fsmc_nor_psram_set_addset(fsmc_nor_psram_reg_map *regs,
+                                             uint8 addset) {
+    regs->BTR &= ~FSMC_BTR_ADDSET;
+    regs->BTR |= addset & 0xF;
+}
 
 #endif /* STM32_HIGH_DENSITY */
 
 #ifdef __cplusplus
-} // extern "C"
+} /* extern "C" */
 #endif
 
 #endif
diff --git a/wirish/native_sram.cpp b/wirish/native_sram.cpp
new file mode 100644
index 0000000..5e8095f
--- /dev/null
+++ b/wirish/native_sram.cpp
@@ -0,0 +1,45 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+#include "native_sram.h"
+#include "libmaple.h"
+#include "fsmc.h"
+#include "rcc.h"
+
+#ifdef BOARD_maple_native
+
+void initNativeSRAM(void) {
+    fsmc_nor_psram_reg_map *regs = FSMC_NOR_PSRAM1_BASE;
+
+    fsmc_sram_init_gpios();
+    rcc_clk_enable(RCC_FSMC);
+
+    regs->BCR = FSMC_BCR_WREN | FSMC_BCR_MWID_16BITS | FSMC_BCR_MBKEN;
+    fsmc_nor_psram_set_addset(regs, 0);
+    fsmc_nor_psram_set_datast(regs, 3);
+}
+
+#endif
diff --git a/wirish/native_sram.h b/wirish/native_sram.h
new file mode 100644
index 0000000..7724667
--- /dev/null
+++ b/wirish/native_sram.h
@@ -0,0 +1,43 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+#ifdef BOARD_maple_native
+
+#ifndef _NATIVE_SRAM_H_
+#define _NATIVE_SRAM_H_
+
+/**
+ * Sets up the FSMC peripheral to use the SRAM chip on the Maple
+ * Native as an external segment of system memory space.
+ *
+ * This implementation is for the IS62WV51216BLL 8Mb chip (55ns
+ * timing, 512K x 16 bits).
+ */
+void initNativeSRAM(void);
+
+#endif
+
+#endif
diff --git a/wirish/rules.mk b/wirish/rules.mk
index cea34f5..3dd4b2d 100644
--- a/wirish/rules.mk
+++ b/wirish/rules.mk
@@ -27,6 +27,7 @@ cppSRCS_$(d) := wirish_math.cpp		 \
 		pwm.cpp 		 \
 		ext_interrupts.cpp	 \
 		wirish_digital.cpp	 \
+		native_sram.cpp		 \
 		boards.cpp
 
 cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%)
diff --git a/wirish/wirish.cpp b/wirish/wirish.cpp
index 6d77bc8..c5a9e30 100644
--- a/wirish/wirish.cpp
+++ b/wirish/wirish.cpp
@@ -41,6 +41,7 @@
 #include "fsmc.h"
 #include "dac.h"
 #include "flash.h"
+#include "native_sram.h"
 
 void init(void) {
     /* make sure the flash is ready before spinning the high speed clock up */
@@ -48,7 +49,7 @@ void init(void) {
     flash_set_latency(FLASH_WAIT_STATE_2);
 
 #ifdef BOARD_maple_native
-    fsmc_native_sram_init();
+    initNativeSRAM();
 #endif
 
     /* initialize clocks  */