fix botched merge from linker-refactor

10 files changed, 876 insertions, 0 deletions

diff --git a/support/ld/flash.ld b/support/ld/flash.ld
new file mode 100644
index 0000000..b66bdef
--- /dev/null
+++ b/support/ld/flash.ld
@@ -0,0 +1,211 @@
+/* Linker script for STM32 (by Lanchon with Mods by LeafLabs)

+ *

+ * Version:Sourcery G++ 4.2-84

+ * BugURL:https://support.codesourcery.com/GNUToolchain/

+ *

+ *  Copyright 2007 CodeSourcery.

+ *

+ * The authors hereby grant permission to use, copy, modify, distribute,

+ * and license this software and its documentation for any purpose, provided

+ * that existing copyright notices are retained in all copies and that this

+ * notice is included verbatim in any distributions. No written agreement,

+ * license, or royalty fee is required for any of the authorized uses.

+ * Modifications to this software may be copyrighted by their authors

+ * and need not follow the licensing terms described here, provided that

+ * the new terms are clearly indicated on the first page of each file where

+ * they apply. */

+

+/* Linker script for STM32 (by Lanchon),

+ * ROM and RAM relocated to their positions 

+ * as placed by Maple bootloader

+ *

+ * Configure target memory and included script

+ * according to your application requirements. */

+

+/* Define memory spaces. */

+MEMORY

+{

+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K

+  rom (rx) : ORIGIN = 0x08005000, LENGTH = 108K

+}

+

+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")

+ENTRY(_start)

+SEARCH_DIR(.)

+/* GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3-lanchon-stm32) */

+GROUP(libgcc.a libc.a libcs3-lanchon-stm32.a)

+

+/* These force the linker to search for particular symbols from

+ * the start of the link process and thus ensure the user's

+ * overrides are picked up

+ */

+EXTERN(__cs3_reset_lanchon_stm32)

+INCLUDE names.inc

+EXTERN(__cs3_interrupt_vector_lanchon_stm32)

+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)

+EXTERN(_start)

+

+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);

+PROVIDE(__cs3_heap_start = _end);

+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);

+

+SECTIONS

+{

+  .text :

+  {

+    CREATE_OBJECT_SYMBOLS

+    __cs3_region_start_rom = .;

+    *(.cs3.region-head.rom)

+    __cs3_interrupt_vector = __cs3_interrupt_vector_lanchon_stm32;

+    *(.cs3.interrupt_vector)

+    /* Make sure we pulled in an interrupt vector.  */

+    ASSERT (. != __cs3_interrupt_vector_lanchon_stm32, "No interrupt vector");

+    *(.rom)

+    *(.rom.b)

+

+    PROVIDE(__cs3_reset_lanchon_stm32 = _start);

+    __cs3_reset = __cs3_reset_lanchon_stm32;

+    *(.cs3.reset)

+

+    *(.text .text.* .gnu.linkonce.t.*)

+    *(.plt)

+    *(.gnu.warning)

+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)

+

+    *(.rodata .rodata.* .gnu.linkonce.r.*)

+

+    *(.ARM.extab* .gnu.linkonce.armextab.*)

+    *(.gcc_except_table)

+    *(.eh_frame_hdr)

+    *(.eh_frame)

+

+    . = ALIGN(4);

+    KEEP(*(.init))

+

+    . = ALIGN(4);

+    __preinit_array_start = .;

+    KEEP (*(.preinit_array))

+    __preinit_array_end = .;

+

+    . = ALIGN(4);

+    __init_array_start = .;

+    KEEP (*(SORT(.init_array.*)))

+    KEEP (*(.init_array))

+    __init_array_end = .;

+

+    . = ALIGN(0x4);

+    KEEP (*crtbegin.o(.ctors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))

+    KEEP (*(SORT(.ctors.*)))

+    KEEP (*crtend.o(.ctors))

+

+    . = ALIGN(4);

+    KEEP(*(.fini))

+

+    . = ALIGN(4);

+    __fini_array_start = .;

+    KEEP (*(.fini_array))

+    KEEP (*(SORT(.fini_array.*)))

+    __fini_array_end = .;

+

+    KEEP (*crtbegin.o(.dtors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))

+    KEEP (*(SORT(.dtors.*)))

+    KEEP (*crtend.o(.dtors))

+

+    . = ALIGN(4);

+    __cs3_regions = .;

+    LONG (0)

+    LONG (__cs3_region_init_ram)

+    LONG (__cs3_region_start_ram)

+    LONG (__cs3_region_init_size_ram)

+    LONG (__cs3_region_zero_size_ram)

+  } >rom

+

+  /* .ARM.exidx is sorted, so has to go in its own output section.  */

+  __exidx_start = .;

+  .ARM.exidx :

+  {

+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)

+  } >rom

+  __exidx_end = .;

+  .text.align :

+  {

+    . = ALIGN(8);

+    _etext = .;

+  } >rom

+

+/* expose a custom rom only section */

+  .USER_FLASH :

+  {

+    *(.USER_FLASH)

+  } >rom

+

+

+  /* __cs3_region_end_rom is deprecated */

+  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);

+  __cs3_region_size_rom = LENGTH(rom);

+  __cs3_region_num = 1;

+

+  .data :

+  {

+    __cs3_region_start_ram = .;

+    *(.cs3.region-head.ram)

+    KEEP(*(.jcr))

+    *(.got.plt) *(.got)

+    *(.shdata)

+    *(.data .data.* .gnu.linkonce.d.*)

+    *(.ram)

+    . = ALIGN (8);

+    _edata = .;

+  } >ram AT>rom

+  .bss :

+  {

+    *(.shbss)

+    *(.bss .bss.* .gnu.linkonce.b.*)

+    *(COMMON)

+    *(.ram.b)

+    . = ALIGN (8);

+    _end = .;

+    __end = .;

+  } >ram AT>rom

+  /* __cs3_region_end_ram is deprecated */

+  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);

+  __cs3_region_size_ram = LENGTH(ram);

+  __cs3_region_init_ram = LOADADDR (.data);

+  __cs3_region_init_size_ram = _edata - ADDR (.data);

+  __cs3_region_zero_size_ram = _end - _edata;

+  __cs3_region_num = 1;

+

+  .stab 0 (NOLOAD) : { *(.stab) }

+  .stabstr 0 (NOLOAD) : { *(.stabstr) }

+  /* DWARF debug sections.

+   * Symbols in the DWARF debugging sections are relative to the beginning

+   * of the section so we begin them at 0.  */

+  /* DWARF 1 */

+  .debug          0 : { *(.debug) }

+  .line           0 : { *(.line) }

+  /* GNU DWARF 1 extensions */

+  .debug_srcinfo  0 : { *(.debug_srcinfo) }

+  .debug_sfnames  0 : { *(.debug_sfnames) }

+  /* DWARF 1.1 and DWARF 2 */

+  .debug_aranges  0 : { *(.debug_aranges) }

+  .debug_pubnames 0 : { *(.debug_pubnames) }

+  /* DWARF 2 */

+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }

+  .debug_abbrev   0 : { *(.debug_abbrev) }

+  .debug_line     0 : { *(.debug_line) }

+  .debug_frame    0 : { *(.debug_frame) }

+  .debug_str      0 : { *(.debug_str) }

+  .debug_loc      0 : { *(.debug_loc) }

+  .debug_macinfo  0 : { *(.debug_macinfo) }

+  /* SGI/MIPS DWARF 2 extensions */

+  .debug_weaknames 0 : { *(.debug_weaknames) }

+  .debug_funcnames 0 : { *(.debug_funcnames) }

+  .debug_typenames 0 : { *(.debug_typenames) }

+  .debug_varnames  0 : { *(.debug_varnames) }

+

+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }

+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }

+  /DISCARD/ : { *(.note.GNU-stack) }

+}

diff --git a/support/ld/jtag.ld b/support/ld/jtag.ld
new file mode 100644
index 0000000..67fbe85
--- /dev/null
+++ b/support/ld/jtag.ld
@@ -0,0 +1,186 @@
+/* Linker script for STM32 (by Lanchon),

+ * ROM and RAM relocated to their positions 

+ * as placed by Maple bootloader

+ *

+ * Configure target memory and included script

+ * according to your application requirements. */

+

+/* Define memory spaces. */

+MEMORY

+{

+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K

+  rom (rx) : ORIGIN = 0x08000000, LENGTH = 120K

+}

+

+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")

+ENTRY(_start)

+SEARCH_DIR(.)

+/* GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3-lanchon-stm32) */

+GROUP(libgcc.a libc.a libcs3-lanchon-stm32.a)

+

+/* These force the linker to search for particular symbols from

+ * the start of the link process and thus ensure the user's

+ * overrides are picked up

+ */

+EXTERN(__cs3_reset_lanchon_stm32)

+INCLUDE names.inc

+EXTERN(__cs3_interrupt_vector_lanchon_stm32)

+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)

+EXTERN(_start)

+

+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);

+PROVIDE(__cs3_heap_start = _end);

+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);

+

+SECTIONS

+{

+  .text :

+  {

+    CREATE_OBJECT_SYMBOLS

+    __cs3_region_start_rom = .;

+    *(.cs3.region-head.rom)

+    __cs3_interrupt_vector = __cs3_interrupt_vector_lanchon_stm32;

+    *(.cs3.interrupt_vector)

+    /* Make sure we pulled in an interrupt vector.  */

+    ASSERT (. != __cs3_interrupt_vector_lanchon_stm32, "No interrupt vector");

+    *(.rom)

+    *(.rom.b)

+

+    PROVIDE(__cs3_reset_lanchon_stm32 = _start);

+    __cs3_reset = __cs3_reset_lanchon_stm32;

+    *(.cs3.reset)

+

+    *(.text .text.* .gnu.linkonce.t.*)

+    *(.plt)

+    *(.gnu.warning)

+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)

+

+    *(.rodata .rodata.* .gnu.linkonce.r.*)

+

+    *(.ARM.extab* .gnu.linkonce.armextab.*)

+    *(.gcc_except_table)

+    *(.eh_frame_hdr)

+    *(.eh_frame)

+

+    . = ALIGN(4);

+    KEEP(*(.init))

+

+    . = ALIGN(4);

+    __preinit_array_start = .;

+    KEEP (*(.preinit_array))

+    __preinit_array_end = .;

+

+    . = ALIGN(4);

+    __init_array_start = .;

+    KEEP (*(SORT(.init_array.*)))

+    KEEP (*(.init_array))

+    __init_array_end = .;

+

+    . = ALIGN(0x4);

+    KEEP (*crtbegin.o(.ctors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))

+    KEEP (*(SORT(.ctors.*)))

+    KEEP (*crtend.o(.ctors))

+

+    . = ALIGN(4);

+    KEEP(*(.fini))

+

+    . = ALIGN(4);

+    __fini_array_start = .;

+    KEEP (*(.fini_array))

+    KEEP (*(SORT(.fini_array.*)))

+    __fini_array_end = .;

+

+    KEEP (*crtbegin.o(.dtors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))

+    KEEP (*(SORT(.dtors.*)))

+    KEEP (*crtend.o(.dtors))

+

+    . = ALIGN(4);

+    __cs3_regions = .;

+    LONG (0)

+    LONG (__cs3_region_init_ram)

+    LONG (__cs3_region_start_ram)

+    LONG (__cs3_region_init_size_ram)

+    LONG (__cs3_region_zero_size_ram)

+  } >rom

+

+  /* .ARM.exidx is sorted, so has to go in its own output section.  */

+  __exidx_start = .;

+  .ARM.exidx :

+  {

+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)

+  } >rom

+  __exidx_end = .;

+  .text.align :

+  {

+    . = ALIGN(8);

+    _etext = .;

+  } >rom

+  /* __cs3_region_end_rom is deprecated */

+  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);

+  __cs3_region_size_rom = LENGTH(rom);

+  __cs3_region_num = 1;

+

+  .data :

+  {

+    __cs3_region_start_ram = .;

+    *(.cs3.region-head.ram)

+    KEEP(*(.jcr))

+    *(.got.plt) *(.got)

+    *(.shdata)

+    *(.data .data.* .gnu.linkonce.d.*)

+    *(.ram)

+    . = ALIGN (8);

+    _edata = .;

+  } >ram AT>rom

+  .bss :

+  {

+    *(.shbss)

+    *(.bss .bss.* .gnu.linkonce.b.*)

+    *(COMMON)

+    *(.ram.b)

+    . = ALIGN (8);

+    _end = .;

+    __end = .;

+  } >ram AT>rom

+  /* __cs3_region_end_ram is deprecated */

+  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);

+  __cs3_region_size_ram = LENGTH(ram);

+  __cs3_region_init_ram = LOADADDR (.data);

+  __cs3_region_init_size_ram = _edata - ADDR (.data);

+  __cs3_region_zero_size_ram = _end - _edata;

+  __cs3_region_num = 1;

+

+  .stab 0 (NOLOAD) : { *(.stab) }

+  .stabstr 0 (NOLOAD) : { *(.stabstr) }

+  /* DWARF debug sections.

+   * Symbols in the DWARF debugging sections are relative to the beginning

+   * of the section so we begin them at 0.  */

+  /* DWARF 1 */

+  .debug          0 : { *(.debug) }

+  .line           0 : { *(.line) }

+  /* GNU DWARF 1 extensions */

+  .debug_srcinfo  0 : { *(.debug_srcinfo) }

+  .debug_sfnames  0 : { *(.debug_sfnames) }

+  /* DWARF 1.1 and DWARF 2 */

+  .debug_aranges  0 : { *(.debug_aranges) }

+  .debug_pubnames 0 : { *(.debug_pubnames) }

+  /* DWARF 2 */

+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }

+  .debug_abbrev   0 : { *(.debug_abbrev) }

+  .debug_line     0 : { *(.debug_line) }

+  .debug_frame    0 : { *(.debug_frame) }

+  .debug_str      0 : { *(.debug_str) }

+  .debug_loc      0 : { *(.debug_loc) }

+  .debug_macinfo  0 : { *(.debug_macinfo) }

+  /* SGI/MIPS DWARF 2 extensions */

+  .debug_weaknames 0 : { *(.debug_weaknames) }

+  .debug_funcnames 0 : { *(.debug_funcnames) }

+  .debug_typenames 0 : { *(.debug_typenames) }

+  .debug_varnames  0 : { *(.debug_varnames) }

+

+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }

+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }

+  /DISCARD/ : { *(.note.GNU-stack) }

+}

diff --git a/support/ld/libcs3-lanchon-stm32.a b/support/ld/libcs3-lanchon-stm32.a
new file mode 100644
index 0000000..4ed858f
--- /dev/null
+++ b/support/ld/libcs3-lanchon-stm32.a
diff --git a/support/ld/libcs3-lanchon-stm32.tar.gz b/support/ld/libcs3-lanchon-stm32.tar.gz
new file mode 100644
index 0000000..5cbcf7d
--- /dev/null
+++ b/support/ld/libcs3-lanchon-stm32.tar.gz
diff --git a/support/ld/names.inc b/support/ld/names.inc
new file mode 100644
index 0000000..a0e1fb2
--- /dev/null
+++ b/support/ld/names.inc
@@ -0,0 +1,61 @@
+/* ISR names for STM32 (by Lanchon) */

+

+EXTERN (__cs3_stack)

+EXTERN (__cs3_reset)

+EXTERN (NMIException)

+EXTERN (HardFaultException)

+EXTERN (MemManageException)

+EXTERN (BusFaultException)

+EXTERN (UsageFaultException)

+EXTERN (__STM32ReservedException7)

+EXTERN (__STM32ReservedException8)

+EXTERN (__STM32ReservedException9)

+EXTERN (__STM32ReservedException10)

+EXTERN (SVCHandler)

+EXTERN (DebugMonitor)

+EXTERN (__STM32ReservedException13)

+EXTERN (PendSVC)

+EXTERN (SysTickHandler)

+EXTERN (WWDG_IRQHandler)

+EXTERN (PVD_IRQHandler)

+EXTERN (TAMPER_IRQHandler)

+EXTERN (RTC_IRQHandler)

+EXTERN (FLASH_IRQHandler)

+EXTERN (RCC_IRQHandler)

+EXTERN (EXTI0_IRQHandler)

+EXTERN (EXTI1_IRQHandler)

+EXTERN (EXTI2_IRQHandler)

+EXTERN (EXTI3_IRQHandler)

+EXTERN (EXTI4_IRQHandler)

+EXTERN (DMAChannel1_IRQHandler)

+EXTERN (DMAChannel2_IRQHandler)

+EXTERN (DMAChannel3_IRQHandler)

+EXTERN (DMAChannel4_IRQHandler)

+EXTERN (DMAChannel5_IRQHandler)

+EXTERN (DMAChannel6_IRQHandler)

+EXTERN (DMAChannel7_IRQHandler)

+EXTERN (ADC_IRQHandler)

+EXTERN (USB_HP_CAN_TX_IRQHandler)

+EXTERN (USB_LP_CAN_RX0_IRQHandler)

+EXTERN (CAN_RX1_IRQHandler)

+EXTERN (CAN_SCE_IRQHandler)

+EXTERN (EXTI9_5_IRQHandler)

+EXTERN (TIM1_BRK_IRQHandler)

+EXTERN (TIM1_UP_IRQHandler)

+EXTERN (TIM1_TRG_COM_IRQHandler)

+EXTERN (TIM1_CC_IRQHandler)

+EXTERN (TIM2_IRQHandler)

+EXTERN (TIM3_IRQHandler)

+EXTERN (TIM4_IRQHandler)

+EXTERN (I2C1_EV_IRQHandler)

+EXTERN (I2C1_ER_IRQHandler)

+EXTERN (I2C2_EV_IRQHandler)

+EXTERN (I2C2_ER_IRQHandler)

+EXTERN (SPI1_IRQHandler)

+EXTERN (SPI2_IRQHandler)

+EXTERN (USART1_IRQHandler)

+EXTERN (USART2_IRQHandler)

+EXTERN (USART3_IRQHandler)

+EXTERN (EXTI15_10_IRQHandler)

+EXTERN (RTCAlarm_IRQHandler)

+EXTERN (USBWakeUp_IRQHandler)

diff --git a/support/ld/ram.ld b/support/ld/ram.ld
new file mode 100644
index 0000000..6398ea4
--- /dev/null
+++ b/support/ld/ram.ld
@@ -0,0 +1,220 @@
+/* Linker script for STM32 (by Lanchon with Mods by LeafLabs)

+ *

+ * Version:Sourcery G++ 4.2-84

+ * BugURL:https://support.codesourcery.com/GNUToolchain/

+ *

+ *  Copyright 2007 CodeSourcery.

+ *

+ * The authors hereby grant permission to use, copy, modify, distribute,

+ * and license this software and its documentation for any purpose, provided

+ * that existing copyright notices are retained in all copies and that this

+ * notice is included verbatim in any distributions. No written agreement,

+ * license, or royalty fee is required for any of the authorized uses.

+ * Modifications to this software may be copyrighted by their authors

+ * and need not follow the licensing terms described here, provided that

+ * the new terms are clearly indicated on the first page of each file where

+ * they apply. */

+

+/* Linker script for STM32 (by Lanchon),

+ * ROM and RAM relocated to their positions 

+ * as placed by Maple bootloader

+ *

+ * Configure target memory and included script

+ * according to your application requirements. */

+

+/* Define memory spaces. */

+MEMORY

+{

+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K

+  rom (rx) : ORIGIN = 0x00000000, LENGTH = 0K

+}

+

+

+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")

+ENTRY(_start)

+SEARCH_DIR(.)

+/* GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3-lanchon-stm32) */

+GROUP(libgcc.a libc.a libcs3-lanchon-stm32.a)

+

+/* These force the linker to search for particular symbols from

+ * the start of the link process and thus ensure the user's

+ * overrides are picked up

+ */

+EXTERN(__cs3_reset_lanchon_stm32)

+INCLUDE names.inc

+EXTERN(__cs3_interrupt_vector_lanchon_stm32)

+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)

+EXTERN(_start)

+

+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);

+PROVIDE(__cs3_heap_start = _end);

+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);

+

+SECTIONS

+{

+  .text :

+  {

+    CREATE_OBJECT_SYMBOLS

+    __cs3_region_start_ram = .;

+    *(.cs3.region-head.ram)

+    __cs3_interrupt_vector = __cs3_interrupt_vector_lanchon_stm32;

+    *(.cs3.interrupt_vector)

+    /* Make sure we pulled in an interrupt vector.  */

+    ASSERT (. != __cs3_interrupt_vector_lanchon_stm32, "No interrupt vector");

+

+    PROVIDE(__cs3_reset_lanchon_stm32 = _start);

+    __cs3_reset = __cs3_reset_lanchon_stm32;

+    *(.cs3.reset)

+

+    *(.text .text.* .gnu.linkonce.t.*)

+    *(.plt)

+    *(.gnu.warning)

+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)

+

+    *(.rodata .rodata.* .gnu.linkonce.r.*)

+

+    *(.ARM.extab* .gnu.linkonce.armextab.*)

+    *(.gcc_except_table)

+    *(.eh_frame_hdr)

+    *(.eh_frame)

+

+    . = ALIGN(4);

+    KEEP(*(.init))

+

+    . = ALIGN(4);

+    __preinit_array_start = .;

+    KEEP (*(.preinit_array))

+    __preinit_array_end = .;

+

+    . = ALIGN(4);

+    __init_array_start = .;

+    KEEP (*(SORT(.init_array.*)))

+    KEEP (*(.init_array))

+    __init_array_end = .;

+

+    . = ALIGN(0x4);

+    KEEP (*crtbegin.o(.ctors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))

+    KEEP (*(SORT(.ctors.*)))

+    KEEP (*crtend.o(.ctors))

+

+    . = ALIGN(4);

+    KEEP(*(.fini))

+

+    . = ALIGN(4);

+    __fini_array_start = .;

+    KEEP (*(.fini_array))

+    KEEP (*(SORT(.fini_array.*)))

+    __fini_array_end = .;

+

+    KEEP (*crtbegin.o(.dtors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))

+    KEEP (*(SORT(.dtors.*)))

+    KEEP (*crtend.o(.dtors))

+

+    . = ALIGN(4);

+    __cs3_regions = .;

+    LONG (0)

+    LONG (__cs3_region_init_ram)

+    LONG (__cs3_region_start_ram)

+    LONG (__cs3_region_init_size_ram)

+    LONG (__cs3_region_zero_size_ram)

+  } >ram

+

+  /* .ARM.exidx is sorted, so has to go in its own output section.  */

+  /* even cs3.rom is in ram since its running as user code under the Maple

+     bootloader */

+  __exidx_start = .;

+  .ARM.exidx :

+  {

+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)

+  } >ram

+  __exidx_end = .;

+  .text.align :

+  {

+    . = ALIGN(8);

+    _etext = .;

+  } >ram

+

+  .cs3.rom :

+  {

+    __cs3_region_start_rom = .;

+    *(.cs3.region-head.rom)

+    *(.rom)

+    . = ALIGN (8);

+  } >ram

+

+  .cs3.rom.bss :

+  {

+    *(.rom.b)

+    . = ALIGN (8);

+  } >ram

+  /* __cs3_region_end_rom is deprecated */

+  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(ram);

+  __cs3_region_size_rom = LENGTH(ram);

+  __cs3_region_init_rom = LOADADDR (.cs3.rom);

+  __cs3_region_init_size_rom = SIZEOF(.cs3.rom);

+  __cs3_region_zero_size_rom = SIZEOF(.cs3.rom.bss);

+

+  .data :

+  {

+

+    KEEP(*(.jcr))

+    *(.got.plt) *(.got)

+    *(.shdata)

+    *(.data .data.* .gnu.linkonce.d.*)

+    *(.ram)

+    . = ALIGN (8);

+    _edata = .;

+  } >ram

+  .bss :

+  {

+    *(.shbss)

+    *(.bss .bss.* .gnu.linkonce.b.*)

+    *(COMMON)

+    *(.ram.b)

+    . = ALIGN (8);

+    _end = .;

+    __end = .;

+  } >ram

+  /* __cs3_region_end_ram is deprecated */

+  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);

+  __cs3_region_size_ram = LENGTH(ram);

+  __cs3_region_init_ram = LOADADDR (.text);

+  __cs3_region_init_size_ram = _edata - ADDR (.text);

+  __cs3_region_zero_size_ram = _end - _edata;

+  __cs3_region_num = 1;

+

+  .stab 0 (NOLOAD) : { *(.stab) }

+  .stabstr 0 (NOLOAD) : { *(.stabstr) }

+  /* DWARF debug sections.

+   * Symbols in the DWARF debugging sections are relative to the beginning

+   * of the section so we begin them at 0.  */

+  /* DWARF 1 */

+  .debug          0 : { *(.debug) }

+  .line           0 : { *(.line) }

+  /* GNU DWARF 1 extensions */

+  .debug_srcinfo  0 : { *(.debug_srcinfo) }

+  .debug_sfnames  0 : { *(.debug_sfnames) }

+  /* DWARF 1.1 and DWARF 2 */

+  .debug_aranges  0 : { *(.debug_aranges) }

+  .debug_pubnames 0 : { *(.debug_pubnames) }

+  /* DWARF 2 */

+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }

+  .debug_abbrev   0 : { *(.debug_abbrev) }

+  .debug_line     0 : { *(.debug_line) }

+  .debug_frame    0 : { *(.debug_frame) }

+  .debug_str      0 : { *(.debug_str) }

+  .debug_loc      0 : { *(.debug_loc) }

+  .debug_macinfo  0 : { *(.debug_macinfo) }

+  /* SGI/MIPS DWARF 2 extensions */

+  .debug_weaknames 0 : { *(.debug_weaknames) }

+  .debug_funcnames 0 : { *(.debug_funcnames) }

+  .debug_typenames 0 : { *(.debug_typenames) }

+  .debug_varnames  0 : { *(.debug_varnames) }

+

+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }

+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }

+  /DISCARD/ : { *(.note.GNU-stack) }

+}

+

diff --git a/support/ld/src.zip b/support/ld/src.zip
new file mode 100644
index 0000000..58ff908
--- /dev/null
+++ b/support/ld/src.zip
diff --git a/support/openocd/flash.cfg b/support/openocd/flash.cfg
new file mode 100644
index 0000000..86020bf
--- /dev/null
+++ b/support/openocd/flash.cfg
@@ -0,0 +1,85 @@
+# script for stm32
+
+interface ft2232
+ft2232_device_desc "Olimex OpenOCD JTAG"
+ft2232_layout olimex-jtag
+ft2232_vid_pid 0x15ba 0x0003
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME stm32
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+# jtag speed speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so ufse F_JTAG = 1MHz
+jtag_khz 1000
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0008
+  # Section 26.6.3
+   set _CPUTAPID 0x3ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+   # FIXME this never gets used to override defaults...
+   set _BSTAPID $BSTAPID
+} else {
+  # See STM Document RM0008
+  # Section 29.6.2
+  # Low density devices, Rev A
+  set _BSTAPID1 0x06412041
+  # Medium density devices, Rev A
+  set _BSTAPID2 0x06410041
+  # Medium density devices, Rev B and Rev Z
+  set _BSTAPID3 0x16410041
+  # High density devices, Rev A
+  set _BSTAPID4 0x06414041
+  # Connectivity line devices, Rev A and Rev Z
+  set _BSTAPID5 0x06418041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+           -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
+           -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
+
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x5000 -work-area-backup 0
+
+flash bank stm32x 0x08000000 0x00020000 0 0 $_TARGETNAME
+
+proc flash_chip {} {
+    echo "Halting..."
+    halt
+    echo "Erasing 128KB..."
+    flash erase_address 0x08000000 0x20000
+    echo "Flashing image..."
+    flash write_bank 0 build/main.bin 0
+    echo "Verifying image..."
+    verify_image build/main.bin 0x08000000 bin
+    echo "Checksum verified, resetting chip"
+    reset run
+    echo "Daemon shutdown"
+    shutdown
+}
+
+init
+flash_chip
diff --git a/support/openocd/run.cfg b/support/openocd/run.cfg
new file mode 100644
index 0000000..234a3c8
--- /dev/null
+++ b/support/openocd/run.cfg
@@ -0,0 +1,75 @@
+# script for stm32
+
+interface ft2232
+ft2232_device_desc "Olimex OpenOCD JTAG"
+ft2232_layout olimex-jtag
+ft2232_vid_pid 0x15ba 0x0003
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME stm32
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+# jtag speed speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so ufse F_JTAG = 1MHz
+jtag_khz 1000
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0008
+  # Section 26.6.3
+   set _CPUTAPID 0x3ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+   # FIXME this never gets used to override defaults...
+   set _BSTAPID $BSTAPID
+} else {
+  # See STM Document RM0008
+  # Section 29.6.2
+  # Low density devices, Rev A
+  set _BSTAPID1 0x06412041
+  # Medium density devices, Rev A
+  set _BSTAPID2 0x06410041
+  # Medium density devices, Rev B and Rev Z
+  set _BSTAPID3 0x16410041
+  # High density devices, Rev A
+  set _BSTAPID4 0x06414041
+  # Connectivity line devices, Rev A and Rev Z
+  set _BSTAPID5 0x06418041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+           -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
+           -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
+
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x5000 -work-area-backup 0
+
+flash bank stm32x 0x08000000 0x00020000 0 0 $_TARGETNAME
+
+proc nopforever {} {
+    puts "Resetting the chip..."
+    reset run
+}
+
+init
+nopforever
diff --git a/support/scripts/copy-to-ide b/support/scripts/copy-to-ide
new file mode 100755
index 0000000..2af1620
--- /dev/null
+++ b/support/scripts/copy-to-ide
@@ -0,0 +1,38 @@
+#!/bin/sh
+
+# This hackish script copies the necessary library files into the Maple IDE
+# repository.
+
+# Change this
+DEST=`pwd`/../maple-ide/hardware/leaflabs/cores/maple/
+
+ARCH=`uname -a`
+
+FILES="LICENSE
+    ./libmaple/*.h
+    ./libmaple/*.c
+    ./libmaple/usb/*.h
+    ./libmaple/usb/*.c
+    ./libmaple/usb/usb_lib/*.h
+    ./libmaple/usb/usb_lib/*.c
+    ./wirish/*.h
+    ./wirish/*.c
+    ./wirish/main.cxx
+    ./wirish/*.cpp
+    ./wirish/comm/*.cpp
+    ./wirish/comm/*.h"
+
+echo "First make sure DEST exists: $DEST"
+if !(test -d $DEST/lanchon-stm32)
+then
+    mkdir $DEST/lanchon-stm32
+fi
+
+echo "Then copy over linker files..."
+cp stm32conf/* $DEST
+cp stm32conf/lanchon-stm32/* $DEST/lanchon-stm32
+
+echo "Finally delete the old and copy the new source files!"
+rm $DEST/*.c $DEST/*.cpp $DEST/*.h $DEST/*.cxx
+cp $FILES $DEST
+echo "Done."