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* parameterize unconstrained timing analysisbryan newbold2013-06-271-2/+3
* fix bugs with trce and parbryan newbold2013-06-271-4/+4
* break out synth_effort as a variablebryan newbold2013-06-271-2/+3
* fix potential problem with old etwr targetbryan newbold2013-06-271-1/+1
* add planahead, fpga_editor, and timing targetsbryan newbold2013-06-271-13/+31
* don't re-coregen after every little Makefile tweakbryan newbold2013-06-191-1/+1
* proper Makefile syntax; device-specific; mcs bitwidthbryan newbold2013-06-191-2/+3
* add 'make lint' verilog-build command; requires verilatorbryan newbold2013-06-051-1/+4
* update with bnewbold's changesbryan newbold2013-03-271-74/+63
* initial colorization stuffbryan newbold2013-03-271-1/+1
* compile in multiple tb-modules (this might slow things down for you)bryan newbold2013-03-211-2/+6
* add .ucf file referencebryan newbold2013-03-211-1/+1
* isim in the background; hackisly fix depsbryan newbold2013-03-201-4/+4
* fixes to simulatebryan newbold2013-03-201-8/+6
* fix ise project pointersbryan newbold2013-03-141-1/+1
* improvementsbryan newbold2013-03-141-12/+20
* some simulation stuffbryan newbold2013-03-131-2/+38
* move stuff around; backupbryan newbold2013-03-131-6/+17
* basic synthesis version of makefilebryan newbold2013-03-131-0/+181
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