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* lint: add color, recursive include, Xilinx primitivesbryan newbold2014-03-241-1/+8
* fix isim target (remove 'simulate')bryan newbold2014-03-241-1/+1
* fix bitfile outputsbryan newbold2014-01-281-1/+2
* buildsys: don't actually need to copy around .ngc'sbryan newbold2013-12-191-3/+2
* buildsys: DEFAULT not DEFAULT_GOALbryan newbold2013-12-191-1/+1
* buildsys: par_ and map_timing PHONY correctionsbryan newbold2013-11-271-1/+1
* allow extending bitfile list on a per-board basisbryan newbold2013-11-241-4/+11
* buildsys: allow sim-only HDL file listsbryan newbold2013-11-211-5/+11
* buildsys: force gmake failure for more targetsbryan newbold2013-11-211-0/+7
* update licensing infobryan newbold2013-11-181-1/+4
* add 'xreport' launcher targetbryan newbold2013-11-131-1/+5
* colorize bitgen errorsbryan newbold2013-11-131-4/+4
* clean up simulation targetsbryan newbold2013-11-131-23/+21
* 'untouchcores' target (see README)bryan newbold2013-11-131-0/+4
* add status messages to bitfile generationbryan newbold2013-11-131-0/+2
* fix bugs with copying _xmsgs to logsbryan newbold2013-11-131-3/+3
* misc small improvementsbryan newbold2013-11-121-5/+17
* rename some targetsbryan newbold2013-11-121-8/+8
* hack fix for bug with include orderingbryan newbold2013-11-121-2/+3
* reorder contrib/xilinx.mk; re-instate ./bitfile/bryan newbold2013-11-121-16/+25
* clean up cleaning (heh)bryan newbold2013-11-121-3/+13
* Part 1 of refactoring template files into ./contribbryan newbold2013-11-121-76/+137
* minor cleanup of lint targetbryan newbold2013-11-121-1/+1
* initial VHDL supportbryan newbold2013-11-121-4/+16
* need to specify .pcf file to bitgen for some casesbryan newbold2013-10-211-1/+1
* partially fix bug where synthesis continues after .ngc failurebryan newbold2013-10-091-0/+2
* clean up test stuffbryan newbold2013-10-081-0/+3
* working xula2 sim/syn/prog systembryan newbold2013-10-081-2/+2
* don't have outputs depend on makefilesbryan newbold2013-10-081-3/+3
* linting: ignore module/filename equivalencebryan newbold2013-10-061-1/+1
* add test/ and isim/ systembryan newbold2013-10-061-12/+34
* add concept of 'board' for seperate ucfs and top level modulesbryan newbold2013-10-041-22/+23
* add autoimpact target (pre-select bitfile)bryan newbold2013-10-041-0/+3
* generic timingan targetbryan newbold2013-10-041-0/+3
* backport improvements from SNG projectbryan newbold2013-10-041-3/+7
* typo: pre-par .ncd file for partial_timing analysisbryan newbold2013-06-271-1/+1
* parameterize unconstrained timing analysisbryan newbold2013-06-271-2/+3
* fix bugs with trce and parbryan newbold2013-06-271-4/+4
* break out synth_effort as a variablebryan newbold2013-06-271-2/+3
* fix potential problem with old etwr targetbryan newbold2013-06-271-1/+1
* add planahead, fpga_editor, and timing targetsbryan newbold2013-06-271-13/+31
* don't re-coregen after every little Makefile tweakbryan newbold2013-06-191-1/+1
* proper Makefile syntax; device-specific; mcs bitwidthbryan newbold2013-06-191-2/+3
* add 'make lint' verilog-build command; requires verilatorbryan newbold2013-06-051-1/+4
* update with bnewbold's changesbryan newbold2013-03-271-74/+63
* initial colorization stuffbryan newbold2013-03-271-1/+1
* compile in multiple tb-modules (this might slow things down for you)bryan newbold2013-03-211-2/+6
* add .ucf file referencebryan newbold2013-03-211-1/+1
* isim in the background; hackisly fix depsbryan newbold2013-03-201-4/+4
* fixes to simulatebryan newbold2013-03-201-8/+6
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