added the base files

5 files changed, 92 insertions, 0 deletions

diff --git a/testbench/fuse.sh b/testbench/fuse.sh
new file mode 100755
index 0000000..ad08c93
--- /dev/null
+++ b/testbench/fuse.sh
@@ -0,0 +1,2 @@
+vlogcomp -prj simulate_isim.prj
+fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o simulate_isim.exe unenclib.tb unenclib.glbl
diff --git a/testbench/signals.wcfg b/testbench/signals.wcfg
new file mode 100644
index 0000000..dbb5e1a
--- /dev/null
+++ b/testbench/signals.wcfg
@@ -0,0 +1,42 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="./isim.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="tb" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="7" />
+   <wvobject fp_name="/tb/project_i/LED_output_2" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">LED_output_2</obj_property>
+      <obj_property name="ObjectShortName">LED_output_2</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb/project_i/Switch_input_0" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">Switch_input_0</obj_property>
+      <obj_property name="ObjectShortName">Switch_input_0</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb/project_i/Switch_input_1" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">Switch_input_1</obj_property>
+      <obj_property name="ObjectShortName">Switch_input_1</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb/project_i/Switch_input_2" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">Switch_input_2</obj_property>
+      <obj_property name="ObjectShortName">Switch_input_2</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb/project_i/Switch_input_3" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">Switch_input_3</obj_property>
+      <obj_property name="ObjectShortName">Switch_input_3</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb/project_i/SYSTEMCLOCK" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">SYSTEMCLOCK</obj_property>
+      <obj_property name="ObjectShortName">SYSTEMCLOCK</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb/project_i/PUSH_BUTTON_RESET_RAW" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">PUSH_BUTTON_RESET_RAW</obj_property>
+      <obj_property name="ObjectShortName">PUSH_BUTTON_RESET_RAW</obj_property>
+   </wvobject>
+</wave_config>
diff --git a/testbench/simulate_isim.exe b/testbench/simulate_isim.exe
new file mode 100755
index 0000000..5e50691
--- /dev/null
+++ b/testbench/simulate_isim.exe
diff --git a/testbench/simulate_isim.prj b/testbench/simulate_isim.prj
new file mode 100644
index 0000000..e610cc5
--- /dev/null
+++ b/testbench/simulate_isim.prj
@@ -0,0 +1,3 @@
+verilog unenclib ../hdl/project.v

+verilog unenclib tb.v

+verilog unenclib /opt/Xilinx/14.3/ISE_DS/ISE/verilog/src/glbl.v

diff --git a/testbench/tb.v b/testbench/tb.v
new file mode 100755
index 0000000..19e07bf
--- /dev/null
+++ b/testbench/tb.v
@@ -0,0 +1,45 @@
+`timescale 1ps/1ps
+module tb;
+
+   reg CLK100;
+always @(CLK100) begin
+    #4980.00 CLK100 <= ~CLK100;
+end
+
+initial begin
+  #0 CLK100 <= 1'b0;  // the first event that sets the clock in motion
+end
+
+
+reg [7:0]  Switch_input;
+wire [7:0] LED_output;
+wire       FPGA_RESET;
+
+project project_i (
+    .PUSH_BUTTON_RESET_RAW(FPGA_RESET),
+    .LED_output_0(LED_output[0]),
+    .LED_output_1(LED_output[1]),
+    .LED_output_2(LED_output[2]),
+    .LED_output_3(LED_output[3]),
+    .LED_output_4(LED_output[4]),
+    .LED_output_5(LED_output[5]),
+    .LED_output_6(LED_output[6]),
+    .SYSTEMCLOCK(CLK100),
+    .Switch_input_0(Switch_input[0]),
+    .Switch_input_1(Switch_input[1]),
+    .Switch_input_2(Switch_input[2]),
+    .Switch_input_3(Switch_input[3])
+  );
+
+
+initial begin
+ #0         Switch_input <= 8'h00;
+ $display("Switch set to zero");
+ #1000000  Switch_input <= 8'h01;
+ $display("Switch set to one");
+ #2000000
+ $display("TEST COMPLETE");
+ $finish();
+end
+
+endmodule