From 0754c0f771c51d48107c5c96d79a512ce56cce0a Mon Sep 17 00:00:00 2001 From: Andrew J Meyer Date: Wed, 6 Mar 2013 18:47:43 -0500 Subject: added the base files --- testbench/fuse.sh | 2 ++ testbench/signals.wcfg | 42 +++++++++++++++++++++++++++++++++++++++++ testbench/simulate_isim.exe | Bin 0 -> 21792 bytes testbench/simulate_isim.prj | 3 +++ testbench/tb.v | 45 ++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 92 insertions(+) create mode 100755 testbench/fuse.sh create mode 100644 testbench/signals.wcfg create mode 100755 testbench/simulate_isim.exe create mode 100644 testbench/simulate_isim.prj create mode 100755 testbench/tb.v (limited to 'testbench') diff --git a/testbench/fuse.sh b/testbench/fuse.sh new file mode 100755 index 0000000..ad08c93 --- /dev/null +++ b/testbench/fuse.sh @@ -0,0 +1,2 @@ +vlogcomp -prj simulate_isim.prj +fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o simulate_isim.exe unenclib.tb unenclib.glbl diff --git a/testbench/signals.wcfg b/testbench/signals.wcfg new file mode 100644 index 0000000..dbb5e1a --- /dev/null +++ b/testbench/signals.wcfg @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + LED_output_2 + LED_output_2 + + + Switch_input_0 + Switch_input_0 + + + Switch_input_1 + Switch_input_1 + + + Switch_input_2 + Switch_input_2 + + + Switch_input_3 + Switch_input_3 + + + SYSTEMCLOCK + SYSTEMCLOCK + + + PUSH_BUTTON_RESET_RAW + PUSH_BUTTON_RESET_RAW + + diff --git a/testbench/simulate_isim.exe b/testbench/simulate_isim.exe new file mode 100755 index 0000000..5e50691 Binary files /dev/null and b/testbench/simulate_isim.exe differ diff --git a/testbench/simulate_isim.prj b/testbench/simulate_isim.prj new file mode 100644 index 0000000..e610cc5 --- /dev/null +++ b/testbench/simulate_isim.prj @@ -0,0 +1,3 @@ +verilog unenclib ../hdl/project.v +verilog unenclib tb.v +verilog unenclib /opt/Xilinx/14.3/ISE_DS/ISE/verilog/src/glbl.v diff --git a/testbench/tb.v b/testbench/tb.v new file mode 100755 index 0000000..19e07bf --- /dev/null +++ b/testbench/tb.v @@ -0,0 +1,45 @@ +`timescale 1ps/1ps +module tb; + + reg CLK100; +always @(CLK100) begin + #4980.00 CLK100 <= ~CLK100; +end + +initial begin + #0 CLK100 <= 1'b0; // the first event that sets the clock in motion +end + + +reg [7:0] Switch_input; +wire [7:0] LED_output; +wire FPGA_RESET; + +project project_i ( + .PUSH_BUTTON_RESET_RAW(FPGA_RESET), + .LED_output_0(LED_output[0]), + .LED_output_1(LED_output[1]), + .LED_output_2(LED_output[2]), + .LED_output_3(LED_output[3]), + .LED_output_4(LED_output[4]), + .LED_output_5(LED_output[5]), + .LED_output_6(LED_output[6]), + .SYSTEMCLOCK(CLK100), + .Switch_input_0(Switch_input[0]), + .Switch_input_1(Switch_input[1]), + .Switch_input_2(Switch_input[2]), + .Switch_input_3(Switch_input[3]) + ); + + +initial begin + #0 Switch_input <= 8'h00; + $display("Switch set to zero"); + #1000000 Switch_input <= 8'h01; + $display("Switch set to one"); + #2000000 + $display("TEST COMPLETE"); + $finish(); +end + +endmodule -- cgit v1.2.3