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author | bryan newbold <bnewbold@leaflabs.com> | 2013-04-26 17:21:01 -0400 |
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committer | bryan newbold <bnewbold@leaflabs.com> | 2013-04-26 17:21:01 -0400 |
commit | b2f0ef5ac43daa2b771dc4a0f06a1ac3d03686de (patch) | |
tree | bd2cf4b12a73edf67eb98ae278bedd21944e8af8 /project.xise | |
parent | 1fcbd96eb7cfe94ef339c4da045f53f777fec073 (diff) | |
download | basic-hdl-template-b2f0ef5ac43daa2b771dc4a0f06a1ac3d03686de.tar.gz basic-hdl-template-b2f0ef5ac43daa2b771dc4a0f06a1ac3d03686de.zip |
update README, comments, .xise project file
Diffstat (limited to 'project.xise')
-rw-r--r-- | project.xise | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/project.xise b/project.xise index 74062fb..16da964 100644 --- a/project.xise +++ b/project.xise @@ -140,9 +140,9 @@ <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Implementation Top" xil_pn:value="Module|project" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|main" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top File" xil_pn:value="../hdl/project.v" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/project" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/> <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> @@ -205,7 +205,7 @@ <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Output File Name" xil_pn:value="project" xil_pn:valueState="default"/> + <property xil_pn:name="Output File Name" xil_pn:value="project" xil_pn:valueState="non-default"/> <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> @@ -219,10 +219,10 @@ <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> - <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="project_map.v" xil_pn:valueState="default"/> - <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="project_timesim.v" xil_pn:valueState="default"/> - <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="project_synthesis.v" xil_pn:valueState="default"/> - <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="project_translate.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="project_map.v" xil_pn:valueState="non-default"/> + <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="project_timesim.v" xil_pn:valueState="non-default"/> + <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="project_synthesis.v" xil_pn:valueState="non-default"/> + <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="project_translate.v" xil_pn:valueState="non-default"/> <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> |