diff options
| -rw-r--r-- | Makefile | 4 | ||||
| -rw-r--r-- | README | 50 | ||||
| -rw-r--r-- | project.xise | 14 |
3 files changed, 56 insertions, 12 deletions
@@ -1,3 +1,5 @@ +# Edit project-specific variables in this file. + project = project top_module = main vendor = xilinx @@ -18,6 +20,8 @@ vfiles = hdl/project.v tbfiles = tb/tb.v # list of .xco files, eg "cores/bram.xco". do not include DCM files. +#xilinx_cores = cores/bram.xco xilinx_cores = +# Bulk of the actual Makefile is in a different file. include ./contrib/xilinx.mk @@ -1,6 +1,38 @@ + A very basic project template for Verilog simulation and synthesis using Isim and Xilinx tools. +Contents: + + hdl/ + Verilog Code + + tb/ + "testbench" simulation code + + docs/ + documentation + + contrib/ + Project-independent build scripts are set here + + backup/ + A handful of old "known-good" bitfiles can get archived here. + + sngdaq.ucf + Wired Leaf pinout definition file + + Makefile + Project-specific build variables are set here + +== HOWTO Build a Bitfile ===================================================== + +The Xilinx ISE development must be installed and licensed on the local machine. +A set of command-line build scripts are usually used to build the project +instead of the ISE IDE, but the later could be configured and used as well. + +Python and GNU make must be on the $PATH. + Build a bitstream (to upload to an FPGA, preconfigured as Spartan 6 chip in Makefile) via: @@ -10,14 +42,12 @@ The toplevel ucf (constraints mapping netlist objects from the verilog compilation to hardware resources, and place and routing and timing constraints) is: - ./project.ucf + ./sngdaq.ucf The toplevel verilog module, which does nothing (just sets some pins to zero) lives in: - ./hdl/project.v - -Add other verilog synthesis (not testbench) files to ./hdl/*.v + ./hdl/sngdaq.v To edit the project with the ISE GUI, try: @@ -31,7 +61,7 @@ Simulate with isim via: make simulate -View the results using the isim GUI with: +View the results using isim with: make isim @@ -42,3 +72,13 @@ signals from your design that are saves in the wcfg. ./testbench/tb.v is the toplevel testbench file for simulation. Please improve and push! + +== HOWTO Coregen ============================================================= + +Run `make coregen` and use the GUI to generate a core. + +Depending on the output, copy .v files to hdl/ and/or .xco files to cores/. +update the Makefile. + +For any .xco files, strip the "Project Options" secion and the final CRC line. + diff --git a/project.xise b/project.xise index 74062fb..16da964 100644 --- a/project.xise +++ b/project.xise @@ -140,9 +140,9 @@ <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Implementation Top" xil_pn:value="Module|project" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top" xil_pn:value="Module|main" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top File" xil_pn:value="../hdl/project.v" xil_pn:valueState="non-default"/> - <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/project" xil_pn:valueState="non-default"/> + <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/> <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> @@ -205,7 +205,7 @@ <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Output File Name" xil_pn:value="project" xil_pn:valueState="default"/> + <property xil_pn:name="Output File Name" xil_pn:value="project" xil_pn:valueState="non-default"/> <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> @@ -219,10 +219,10 @@ <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> - <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="project_map.v" xil_pn:valueState="default"/> - <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="project_timesim.v" xil_pn:valueState="default"/> - <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="project_synthesis.v" xil_pn:valueState="default"/> - <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="project_translate.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="project_map.v" xil_pn:valueState="non-default"/> + <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="project_timesim.v" xil_pn:valueState="non-default"/> + <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="project_synthesis.v" xil_pn:valueState="non-default"/> + <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="project_translate.v" xil_pn:valueState="non-default"/> <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> |