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author | bryan newbold <bnewbold@leaflabs.com> | 2013-10-09 00:30:58 -0400 |
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committer | bryan newbold <bnewbold@leaflabs.com> | 2013-10-09 00:30:58 -0400 |
commit | 58a4d81047891bf2bcfaa141f81b4ea34f0c3594 (patch) | |
tree | 189f4c6fc36d215326aa0c25a8195d97b027dfa9 /hdl | |
parent | 3589de222db1820a48fcee63c9516e0347fac7c5 (diff) | |
download | basic-hdl-template-58a4d81047891bf2bcfaa141f81b4ea34f0c3594.tar.gz basic-hdl-template-58a4d81047891bf2bcfaa141f81b4ea34f0c3594.zip |
fix up minor xula2 typos
Diffstat (limited to 'hdl')
-rw-r--r-- | hdl/main_xula2.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hdl/main_xula2.v b/hdl/main_xula2.v index 49581e1..4436665 100644 --- a/hdl/main_xula2.v +++ b/hdl/main_xula2.v @@ -36,7 +36,7 @@ module main ( wire [7:0] rx_byte; wire [7:0] tx_byte; wire uart_flag; - simple_uart ( + simple_uart #( .CLOCK_DIVIDE(313) // for 12MHz clock ) simple_uart_inst ( .clk(clock_12mhz), |