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| author | bryan newbold <bnewbold@leaflabs.com> | 2013-11-12 18:25:21 -0500 |
|---|---|---|
| committer | bryan newbold <bnewbold@leaflabs.com> | 2013-11-12 18:27:08 -0500 |
| commit | 03e710c5a2e75b889550f06852e87c2f869ea152 (patch) | |
| tree | bf06568cce33f04439fc2db179052f86160f7cb7 /README | |
| parent | 3a8d5749a393b1a8b462ec5babf757d693419393 (diff) | |
| download | basic-hdl-template-03e710c5a2e75b889550f06852e87c2f869ea152.tar.gz basic-hdl-template-03e710c5a2e75b889550f06852e87c2f869ea152.zip | |
fix typos revealed by going through QUICK_START
Diffstat (limited to 'README')
| -rw-r--r-- | README | 10 |
1 files changed, 7 insertions, 3 deletions
@@ -1,5 +1,5 @@ -* * < DELTEME > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * +* * * DELETE ME * * * * * * * DELETE ME * * * * * * * DELETE ME * * * * * * * * This folder contains a template Verilog/VHDL HDL project with a basic build system for using the Xilinx ISE toolchain to target FPGAs. @@ -10,11 +10,15 @@ minimum you will need to copy ./contrib/Makefile.example to ./Makefile. Hint: search this file for "<board>" -* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * +^ ^ ^ DELETE ME ^ ^ ^ ^ ^ ^ ^ DELETE ME ^ ^ ^ ^ ^ ^ ^ DELETE ME ^ ^ ^ ^ ^ ^ ^ ^ == About ===================================================================== -<fill this part in> + + + <<<<fill this part in>>>> + + See COPYING for copyright and licensing information. |